Abstract: In a power semiconductor device 10, a continuous trench has an outer circumferential portion 58 that includes a field plate and inner portions 28 that carry include one or more gate runners 34 to that the gate runners and the field plate are integral with each other. The trench structure 58, 28 is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.

Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.

Abstract: A method of analyzing electrocardiogram (ECG) data, including data derived from a paper chart, includes the steps of providing ECG data to create a computer-readable ECG data file representative of the ECG chart, storing the ECG data file in a memory of a computer, opening the ECG data file and displaying on a computer display an ECG plot corresponding to the ECG data file, calibrating the x-axis and y-axis of the displayed ECG plot with an x-axis scale and a y-axis scale, identifying characteristics of the ECG plot by using an input device connected to the computer, and measuring the identified characteristics.

Abstract: An integrated circuit (IC) configured for being connected to an external reference voltage uses an IC reference voltage to determine the logic levels of signals applied to the IC. The IC includes an internal reference voltage generator and logic for selecting one of the internal reference voltage and the external reference voltage for use as the IC reference voltage dependent at least in part upon the operational mode of the IC.