Abstract: A programmable logic device (PLD) includes configuration circuitry. The configuration circuitry is adapted to receive serial configuration data from a configuration device. The configuration circuitry is further adapted to program a function of the PLD without using an input buffer to store the configuration data.

Abstract: A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.

Abstract: An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.

Abstract: Apparatus and methods are disclosed for improving the performance of a programmable logic device (PLD). A PLD includes a memory cell configured to provide a pair of voltages to a gate of a pass transistor and a body of the pass transistor, respectively.

Abstract: A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the reference voltage and a voltage derived from the output current. A low-noise voltage reference circuitry includes a reference voltage source, a voltage source, and a controller. The reference voltage source generates a reference voltage. The voltage source provides a low-noise output voltage in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the output voltage and the reference voltage.

Abstract: Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The interface between the receiver analog circuitry and the receiver digital circuitry includes configurable signal lines that function as a serial interface, or as a data and clock signal interface, depending on the state of a control signal.

Abstract: A buffer circuitry buffers a radio-frequency (RF) signal. The buffer circuitry includes a complementary pair of switches and a power source. The a complementary pair of switches has an input terminal and output terminal. The input terminal of the complementary pair of switches responds to the RF signal. The output terminal of the complementary pair of switches couples to an output of the buffer circuitry. The power source includes a capacitor coupled to a current source. The power source couples to the complementary pair of switches. The power source supplies power to the complementary pair of switches in a manner that the buffer circuitry supplies a substantially constant power level at its output.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A radio-frequency (RF) apparatus capable of transmitting RF signals includes transmitter path circuitry. The transmitter path circuitry includes a voltage-controlled oscillator (VCO) that generates an output signal. The frequency of the output signal of the VCO circuitry is adjustable in response to a first control signal and a second control signal. The transmitter path circuitry also includes a first feedback circuitry and a second feedback circuitry that are responsive to the output signal of the VCO circuitry. The first feedback circuitry provides the first control signal to the VCO circuitry. The first control signal coarsely adjusts the frequency of the output signal of the VCO circuitry to a desired frequency. The second feedback circuitry supplies the second control signal to the VCO circuitry. The second control signal fine tunes the frequency of the output signal of the voltage-controlled oscillator circuitry to the desired frequency.

Abstract: An integrated circuit (IC) includes a ring oscillator. One may tune the ring oscillator by controlling a power supply of the ring oscillator. One may further tune ring oscillator by varying a capacitance of at least one varactor. Using the tuning techniques, one may tune the output frequency of the ring oscillator to a desired frequency.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.