Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A tone detector includes at least one circuit (hereinafter “single phase reference matcher”) that not only performs a convolution of an input signal with a reference signal, but also compares the result of convolution with a threshold to determine if there is a match, and if so drives a signal active indicating that tone is present. If there is no match, another circuit (hereinafter “phase shifter”) delays the reference signal by a fraction (e.g. ⅛) of the measuring period, thereby to introduce a phase shift (e.g. &pgr;/8) between the input signal and the reference signal. The “single phase reference matcher” again performs the just-described operation, this time with a delayed reference signal, and repeats the operation as often as necessary (e.g. eight times) to cycle through the entire measuring period, thereby to ensure that tone (if present in the input signal) is detected irrespective of phase, during one of the operations.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A system that can be dynamically configured to achieve an optimal routing path for an end-to-end data link connection is disclosed. An optimal data path can be determined by a digital subscriber loop (DSL) user based on particular bandwidth requirements, data rate cost constraints, and/or data delay requirements. The data path can be set up to include one or more data routes, including the regular digital public switching telephone network (PSTN), a wide area networks (WAN), or virtual permanent circuit links via digital cross-connects (DCS).

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A number of novel new devices and circuits are disclosed utilizing configurable magneto-electronic elements such as magnetic spin transistors and hybrid hall effect devices. Such magneto-electronic elements can be used as building blocks of an entirely new family of electronic devices for performing functions not easily implementable with semiconductor based device. A number of examples are provided, including logic gates that can be programmed to perform different boolean logic operations at different periods of time. Logic devices and circuits incorporating such logic gates have a number of operational advantages and benefits over conventional semiconductor based technologies, including the fact that traditional signal logic operations can be implemented with substantially fewer active elements.

Abstract: Frame synchronization between Asymmetric Digital Subscriber Line (ADSL) transceivers operating using Discrete Multi-tone (DMT) line code is effectuated by boundary detection logic executing a rapid, computationally simple correlation process. The invention is particularly suited for ADSL software modem implementations, where conservation of computing resources is especially critical, and loss of synchronization can lead to significant unrecoverable data errors.

Abstract: An improved address translation method and mechanism for memory management in a computer system is disclosed. A fast physical address is generated in parallel with a fully computed virtual-linear-physical address in a system using segmentation and optional paging. This fast physical address is used for a tentative or speculative memory reference, which reference can be canceled in the event the fast physical address does not match the fully computed address counterpart. In this manner, memory references can be accelerated in a computer system by avoiding a conventional translation scheme requiring two separate and sequential address translation operations—i.e. from virtual to linear, and from linear to physical.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A new type of magneto-electronic element, such as a spin transistor or hybrid hall effect device, can be used to construct memory systems to replace conventional cache, primary, secondary and long term (archival) storage. The magneto-electronic element is non-volatile, and has switching speeds and integration densities that compare favorably with conventional semiconductor random access memories, such as DRAM. In another embodiment, an integrated memory system may be constructed that synthesizes one or more previously disparate levels of conventional memory (i.e., a combination of primary and secondary storage) so that memory organization is further simplified and performance and cost are improved.