Abstract: A common-path, point-diffraction, phase-shifting interferometer uses a half wave plate having a diffractive element, such as pin hole. A coherent, polarized light source simultaneously generates a reference beam from the diffractive element and an object beam from remaining portions of the light going through the half wave plate. The reference beam has a nearly spherical wavefront. Each of the two beams possesses a different polarization state. The object and reference beams are then independently phase modulated by a polarization sensitive phase modulator that shifts phase an amount depending on applied voltage and depending on polarization state of the incident light. A polarizer is then used to provide the object and reference beams in the same polarization state with equal intensities so they can interfere to create an interferogram with near unity contrast.

Abstract: A common-path, point-diffraction, phase-shifting interferometer uses a half wave plate having a diffractive element, such as pin hole. A coherent, polarized light source simultaneously generates a reference beam from the diffractive element and an object beam from remaining portions of the light going through the half wave plate. The reference beam has a nearly spherical wavefront. Each of the two beams possesses a different polarization state. The object and reference beams are then independently phase modulated by a polarization sensitive phase modulator that shifts phase an amount depending on applied voltage and depending on polarization state of the incident light. A polarizer is then used to provide the object and reference beams in the same polarization state with equal intensities so they can interfere to create an interferogram with near unity contrast.

Abstract: A method and system for finding and setting the illumination in a projection imaging system to achieve optimum imaging. The global optimum illumination is found based on the desired characteristics of the image irradiance distribution as embodied in a target aerial image. The system employs an optimization algorithm that finds the best combination of projected mask images, each such image formed by directing source illumination to selected regions (e.g., pixels) in the entrance pupil (each such region location and size corresponding to a nominal illumination direction and a particular range of angles about the nominal). The optimum illumination is defined as that illumination which produces an aerial image closest to the predefined target aerial image. The system then sets the illuminator to produce the source distribution necessary to achieve this optimal illumination.

Abstract: A multiple clock translator for a microprocessor is provided for synchronizing data from an external clock speed to an internal clock speed that is a non-integer multiple of the external clock speed. The translator comprises a latch circuit and a synchronization signal generator. The latch circuit receives data at the external clock speed and outputs data at the internal clock speed. The latch circuit includes an input latch and a sync latch, and receives an external clock having an enabling phase and an internal clock having an enabling phase. The input latch is docked by the enabling phase of the external clock, and the sync latch is docked by the enabling phase of the internal clock and enabled by a sync pulse. The synchronization signal generator generates a series of sync pulses that are output to the latch circuit in a selected pattern, wherein the pattern is a function of the non-integer multiple.

Abstract: An apparatus (20) for monitoring the trench formation process in a silicon wafer on a full in-situ and on-line basis. The apparatus includes two spectrometers (30A, 30B) for viewing the plasma used in the trench etching process at zero and normal angles of incidence with respect to the plane of the wafer, respectively. Both spectrometers are tuned to detect the radiation associated with a selected specie present in the plasma. Based on information contained in the output signals of the spectrometers, the depth D of the trench and the thickness Th and rate of deposition of the redeposited SiO.sub.2 layer are computed in real time. When the computed depth D matches a final depth of parameter, the trench formation process is terminated.

Abstract: An air mixer cool plate (100) for dissipating heat from a plurality of heat-generating elements (22) positioned in an air stream (26). The plate is made from a material having a thermal conductivity preferably ranging from 1 to 500 watts/meter-K and is designed to be positioned to contact the top surfaces of the heat-generating elements. The plate includes a plurality of apertures (106, 108) and a plurality of upstanding air deflectors (110). The apertures and deflectors are arranged so that when the plate is supported in predetermined relation to the heat-generating elements and the air stream, the plate will cause the air stream to be deflected so as to flow in intimate contact with the elements, thereby carrying heat away from the elements by convection and conduction.

Abstract: A method of forming rim type phase-shift lithography mask (140) involving backside overexposure of a positive resist layer (130) overlying a patterned light-blocking layer (120). By subjecting the resist layer to electromagnetic radiation (132) (e.g., broad band UV) transmitted via the backside (115) of the mask substrate (112), portions (134) of the resist layer extending from peripheral edges of the light blocking layer inwardly a selected distance are activated. After developing activated portions of the resist layer, the "pull back" of the resist layer is transferred to the underlying light blocking layer by anisotropically etching portions of the light blocking layer not covered by the resist layer, thereby forming the desired rim structure.

Abstract: A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).

Abstract: Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.

Abstract: An exhaust system for use with a high temperature furnace used to perform oxidation and/or annealing operations of the type used in semiconductor fabrication. The exhaust system is designed to permit the furnace to be used with a controlled environment chamber surrounding the entry to the process chamber of the furnace. The exhaust system allows a relatively high velocity flow of exhaust gas from the process chamber through the exhaust system to occur when a positive pressure (e.g., annealing) operations are performed. Such high velocity flow prevents (a) backstreaming and (b) the accumulation of non-uniform concentrations of exhaust gases in the exhaust system, thereby permitting the accurate monitoring of the concentration of a selected gas in the exhaust system. Based on such monitoring, the opening of the door to the process chamber of the furnace may be prevented when the concentration of the selected gas exceeds a predetermined level.

Abstract: A modular multilayer interwiring structure comprising a plurality of relatively small parts which are produced separately as `sub-units` (1). Each individual layer of the final structure is formed by joining a respective set of unit parts in one plane. The whole multilayer structure is then built by stacking these layers, preferably so that the units of one layer are not vertically aligned with the units of an adjacent layer. Each unit part includes at least one layer of conductive material (8, 9) on its front and/or rearside. These conductive layers may be individually patterned into diverse interconnection lines (5). Throughconnections (6) extending from the frontside to the backside of the units are provided using a desired set or a standardized array of via holes or openings filled with conductive material. By connecting desired throughconnections to the respective conduction lines, each unit may form an individual part of a more complex multilayer interwiring structure.

Abstract: A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available.