Abstract: A microcontroller integrates a memory accessible by the cores included thereon. Additionally the microcontroller provides an indication upon an external bus that accesses to the integrated memory are occurring. The indication provides a ready identification of internal access cycles. In one embodiment, the indication is multiplexed with a control signal upon the external bus. The microcontroller further employs a show read bus transfer, which may be optionally enabled by the user. The show read bus transfer transmits upon the external bus the read data being provided from the internal memory to a core. The cycle is presented with identical functional timing to normal read cycles. Additionally, the A/C timings of the show read bus transfer are consistent with external read transfers. Therefore, external circuitry (such as an in-circuit emulator) may capture the data from the show read bus transfer using the same circuitry used to capture external read data.

Abstract: A personal information device is provided, which includes an integrated circuit coupled to a variety of peripheral devices. The integrated circuit is configured with a core section and one or more input/output sections. The core section is powered independently of the input/output sections, allowing selective power down of peripheral components coupled to the integrated circuit without the use of external buffers. The input/output sections are configured with unique input/output circuits which perform the buffering task. The integrated circuit is further configured with a partial reset. The partial reset selectively forces portions of the integrated circuit to an initial state while other portions continue to operate. One particular embodiment of the integrated circuit is configured with a CPU and an RTC unit which comprises configuration RAM and a real time clock facility. When the partial reset is activated, the RTC unit is not reset but the CPU is reset.

Abstract: An integrated circuit is provided which comprises a core section, a plurality of input/output sections, and a pair of reset inputs. The first reset input is a master reset which initializes the entire integrated circuit. The second reset input is a partial reset. The partial reset initializes a portion of the integrated circuit while other portions remain in operation. The core section can include a plurality of subsystems such as a real time clock facility, a configuration RAM, and a DRAM memory controller. The real time clock facility and configuration RAM are not affected by the partial reset. Accordingly, the real time clock is maintained during partial reset, thereby maintaining accurate time/date and configuration data during partial reset. The DRAM controller is optionally reset based on a configuration bit stored in a configuration register in one of the plurality of subsystems.

Abstract: Two embodiments of a digital signal processor are described. Each embodiment is configured with an instruction processing pipeline including an execute-write pipeline stage. When an instruction reaches the execute-write pipeline stage, the instruction is executed and the corresponding result is written to the specified destination. Additionally, the execute-write stage maintains a relatively short pipeline. One embodiment described herein employs an instruction set in which the destination of an instruction may be encoded within a subsequent instruction. The number of bits utilized to encode a particular instruction is reduced by the number of bits that would have specified the destination.

Abstract: A remote access system remotely accesses one or more electronic locks from a locally placed computer. The computer includes a key receptacle electrically coupled to the computer. The key receptacle allows ingress of a key, whereupon insertion of the key and login permission granted allows access of the computer to an electronic lock via a communication channel. The electronic lock is mechanically, electrically and functionally connected to activate and deactivate a locking mechanism of a lockable device. According to one arrangement, the computer is connected to the electronic lock via the communication channel to allow the user remote login to the electronic lock. The user located remote from the lock may therefore operate the lock from the remote location.

Abstract: A programmable electronic lock is provided. The electronic lock described herein employs many programmable features which enable a user to tailor lock functions for appropriate levels of security and convenience. The features are enabled and tailored via a set of operating parameters stored in an operating parameters data base within the lock. A lockable device employing the present lock may achieve levels of security and flexibility greater than those achieved utilizing conventional locks. Several of the features included in the lock are a timelock early feature for securing the lock prior to a programmed locking time; an idle key life feature for deactivating idle keys from the lock; a variable PIN code requirement structure for convenience and security; and a deposit logging feature for deposit doors.

Abstract: A voltage controlled oscillator circuit with a high power supply rejection ratio incorporates a clamping transistor with respect to each output terminal which limits the signal swing of the output terminal. The limited voltage swing allows relatively large movements in the power supply and ground voltages without causing significant changes in the frequency of the output signals. Such an oscillator circuit may be incorporated into an integrated circuit characterized by noisy power supply and ground conductors. Additionally, multiple delayed versions of the output frequency may be created using a level shifter circuit and a buffer circuit. The oscillator circuit is relatively quick to react to changes in the controlling voltage, adjusting the oscillation frequency in a relatively short time interval.