Patents Represented by Attorney Lawwrence J. Bassuk

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  • Memory access circuits for test time reduction
    Patent number: 5910923
    Abstract: Testing of an integrated circuit having arrays of memory cells occurs by writing to all of the arrays at the same time. Normal writing occurs only to one array. Additional test data bus leads on the chip carry test data signals from selected arrays to comparison circuits. The outputs of the comparison circuits flow to the output circuits of the chip. This achieves writing test data to four times the number of arrays as in a normal write and reading test data from twice the number of arrays as in a normal read operation.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: June 8, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Brian L. Brown, David R. Brown, Daniel B. Penney, Roger D. Norwood