Abstract: An apparatus for searching for a cell and a method of acquiring a code unique to each cell in an asynchronous wideband Direct-Sequence Code Division Multiple Access (DS/CDMA) receiver, wherein the cell searching apparatus searches for a cell based on a received asynchronous wideband DS/CDMA signal in a receiver, the apparatus including a code group identifying unit for estimating and compensating for a frequency error between the synchronous channel and an internally generated primary synchronization code, estimating and compensating for channel degradation which the synchronous channel has experienced, and performing correlation on the compensated synchronous channel and available secondary synchronization codes, thereby identifying the code group; and a scrambling code identifying unit for performing correlation on a plurality of scrambling codes belonging to the code group, thereby obtaining a scrambling code unique to each cell.

Abstract: An apparatus for drying a substrate using an isopropyl alcohol vapor includes a container for receiving an isopropyl alcohol vapor to dry a plurality of substrates wherein an opening is vertically formed through an upper portion of the container to permit the loading and unloading of the substrates; a supporting member for supporting the plurality of substrates in the container in a vertical direction and for supporting the substrates side by side in a horizontal direction, wherein the supporting member extends through the container and through the opening; and a cover for obstructing a flow of clean air from flowing directly from an air cleaner disposed over the container into the container through the opening. In addition, the apparatus may include an inert gas supplying member to supply an inert gas onto the substrates to prevent native oxide films from forming on the substrates.

Abstract: A wavelength-selective photo detector device includes a transparent upper electrode including a capacitor, a first semiconductor layer disposed under the upper electrode, an optical absorption layer disposed under the first semiconductor layer for absorbing light to form pairs of electrons and holes, an amplification layer disposed under the optical absorption layer for generating secondary electrons, a second semiconductor layer disposed under the amplification layer, and a lower electrode disposed under the second semiconductor layer and including an inductance coupled in parallel with an external resistance. The photo detector improves the S/N ratio and filters only light having a particular wavelength band.

Abstract: A method of forming a magnetic tunneling junction (MTJ) layer for an MRAM includes sequentially forming a lower material layer, an insulation layer, and an upper material layer on a substrate, forming a mask pattern on a predetermined region of the upper material layer, sequentially removing the upper material layer, the insulation layer, and the lower material layer from around the mask pattern using plasma generated from an etching gas, wherein the etching gas is a mixture of a main gas and an additive gas having a predetermined mixture ratio and including no chlorine (Cl2) gas, and removing the mask pattern. Accordingly, an MTJ layer formed by the method may incur no thermal damage due to high temperature etching, no material deposits due to by-products of etching, and no step difference or corrosion due to chlorine gas, and may have an excellent profile.

Abstract: A side-bonding method of a flip-chip semiconductor device, a MEMS device package and a package method using the same, in which firm bonding and insensitivity to surface roughness may be obtained, include forming a UBM on a bonding line of a lower substrate having a semiconductor device formed thereon, plating solder on the UBM on the lower substrate, forming a trench in the upper substrate to contact the lower substrate at a location corresponding to a location of the solder and forming a second UBM in the trench, coupling the upper substrate and the lower substrate by inserting the solder into the trench, and heating the upper substrate and the lower substrate at a temperature higher than a melting point of the solder so that the solder is wetted toward sides of the trench to bond the upper substrate and the lower substrate.

Abstract: A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.

Abstract: A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.

Abstract: A split gate memory device and fabricating method thereof, wherein gate insulating and polysilicon layers are sequentially formed on a substrate. The polysilicon layer is patterned and a capping insulating layer is formed on portions thereof. A pair of self-aligned control gates having identical bottom widths are formed with a tunnel insulating layer interposed between the control gates and sidewalls of the polysilicon layer pattern and capping insulating layer. The tunnel insulating layer, patterned polysilicon layer and gate insulating layer are selectively etched to expose a portion of the substrate thereby forming a pair of floating gates. Ions are implanted into the exposed substrate and portions of the substrate adjoining the control gates to form a common source region and a drain region, respectively. The capping insulating layer on the floating gate protects an acute section of the tunnel insulating layer from attack during the etching and ion implantation.

Abstract: A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

Abstract: A photolithography processing system includes a table for supporting a wafer, a plurality of illumination tools for illuminating a surface of the wafer positioned on the table, including a plurality of first illumination tools positioned laterally at different heights to illuminate the surface of the wafer at various predetermined angles of incidence and a second illumination tool to illuminate the surface of the wafer vertically from above the wafer on the table, a camera for taking pictures of the surface of the wafer, and a controller for controlling operations of the robot, the plurality of illumination tools and the camera and for detecting the presence of impure matters on the surface of the wafer, the controller including an elevating unit to slide up or down the first illumination tools and a luminous intensity unit to control luminous intensity.

Abstract: Disclosed are a method and an apparatus for processing a wafer in manufacturing a semiconductor device and a method and an apparatus for etching a material formed on the wafer, wherein first and second cooling parts adjust an ambient temperature near a plurality of wafers to a first temperature, the wafers are processed by introducing a reaction gas at the first temperature, then, a heating part rapidly raises the temperature of the atmosphere near the wafers from the first temperature to the second temperature to partially separate by-products produced during the processing, the second temperature is maintained to separate most of the by-products from the wafers, and the processing steps are implemented in-situ within the same space. Accordingly, a native oxide layer formed on several wafers can be etched and the reaction by-products can be removed in-situ in the same chamber so productivity is improved.

Abstract: An electron-beam focusing apparatus for controlling a path of electron beams emitted from an electron-beam emitter in an electron-beam projection lithography (EPL) system includes top and bottom magnets for creating a magnetic field within a vacuum chamber, the top and bottom magnets disposed above and below the vacuum chamber into which a wafer is loaded, respectively; upper and lower pole pieces magnetically contacting the top and bottom magnets, respectively, the upper and lower pole pieces penetrating a top wall and a bottom wall of the vacuum chamber, respectively; and upper and lower projections having a circular shape, extending outwardly from facing surfaces of the upper and lower pole pieces, respectively.

Abstract: In a mode entrance control circuit and a mode entering method to stably enter a semiconductor memory device into a predetermined operating mode only when insensitive to a change of a process, temperature, or voltage, etc., and simultaneously satisfying a constant entrance condition, the mode entrance control circuit includes an operation control part for generating an operation enable signal when a first voltage applied through a first pad is over a first determination voltage, a voltage division part for dividing a second voltage applied through a second pad to generate a trimming reference voltage, and a mode entrance signal generating part operated in response to the operation enable signal, for comparing a level of an applied fixed reference voltage with a level of the trimming reference voltage, and for generating a mode entrance enable signal to allow the semiconductor memory device to enter into a predetermined mode.

Abstract: A bubble-jet type ink-jet printhead and manufacturing method thereof including a substrate integrally having an ink supply manifold, an ink chamber, and an ink channel; a nozzle plate having a nozzle on the substrate; a heater centered around the nozzle and an electrode for applying current to the heater on the nozzle plate; and an adiabatic layer on the heater for preventing heat generated by the heater from being conducted upward from the heater. Alternatively, a bubble-jet type ink-jet printhead may be formed on a silicon-on-insulator (SOI) wafer having a first substrate, an oxide layer, and a second substrate stacked thereon and include an adiabatic barrier on the second substrate. In the bubble-jet type ink-jet printhead and manufacturing method thereof, the adiabatic layer or the adiabatic barrier is provided to transmit most of the heat generated by the heater to ink under the heater, thereby increasing energy efficiency.

Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

Abstract: A microgyroscope tunable against an external translational acceleration includes an oscillating mass floating over a wafer to oscillate in a first direction, a driving electrode for oscillating the oscillating mass, a sensing mass oscillating together with the oscillating mass and concurrently moving in a second direction, wherein the second direction is perpendicular to the first direction, a sensing electrode for sensing a motion of the sensing mass, and a sensing electrode supporting portion for movably securing the sensing electrode so that the sensing electrode can move in the second direction with the sensing mass. A microgyroscope according to the present invention is able to prevent sensing signals due to an external disturbance, such as noise or impulse.

Abstract: An output control signal generating circuit in a synchronous semiconductor memory device preferably comprises 1) a plurality of selectable clock signal transfer circuits for selectively delaying an applied clock signal in order to generate an output control clock signal in response to a predetermined CAS latency signal, wherein each one of the plurality of selectable clock signal transfer circuits inserts one or more time delays into the output control clock signal, 2) a sampling circuit for generating a plurality of output signals from a read master signal, and 3) a selection circuit for selecting one of plurality of output signals, thereby indicating a valid data output time interval. A method for operating the output control signal generating circuit causes a clock signal to be delayed by a selectable number of additional clock cycles, thereby insuring the outputting of a data signal only at a time when the data is valid.

Abstract: A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.