Abstract: A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder of the register file in response to a power-down condition. The power-down condition occurs when, for example, no valid address is driven to the read port, i.e. the read port is unused. For one embodiment of the invention, the selected entry is the zeroth entry of the register file, and the address lines are grounded when an address valid bit associated with the read port is not asserted.

Abstract: The present invention provides a digital-based mechanism for adjusting the power consumption in an integrated digital circuit such as a processor. The processor includes one or more functional units and a digital throttle that monitors activity states of the processor's functional units to estimate the processor's power consumption. One embodiment of the digital throttle includes one or more gate units, a monitor circuit, and a throttle circuit. Each gate unit controls the delivery of power delivery to a functional unit of the processor and provides a signal that indicates the activity state of its associated functional unit. The monitor circuit determines an estimated power consumption level from the signals and compares the estimated power consumption with a threshold power level. The throttle circuit adjusts the instruction flow in the processor if the estimated power consumption level exceeds the threshold power level.

Abstract: A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

Abstract: A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

Abstract: A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.

Abstract: A system for processing caches misses includes a request miss buffer, secondary miss logic, and a request identifier buffer. When a request misses in a cache, information characterizing the request is provided to the request miss buffer and the secondary miss logic. The secondary miss logic determines whether the request may be merged with a pending bus transaction, and provides the request identifier buffer with a pointer to the request information. The pointer is stored at an entry associated with the pending bus transaction. For a load request, data returned by the bus transaction is routed to a targeted register, using the request information in the request miss buffer.

Abstract: A system for storing data on a magnetic medium using spin polarized electron beams is provided. The system includes a source of spin polarized electrons and a storage medium disposed a selected distance from the source. The storage medium has a plurality of storage locations, each of which includes a layer of magnetic material sandwiched between first and second layers of a half-metallic material. The resulting sandwich structure forms a spin dependent electron trap that increases coupling between beam electrons in a first spin state and target electrons in a second spin state. An electron optics system directs the source of spin polarized electrons to one of the plurality of storage locations.

Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.

Abstract: The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.

Abstract: A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines target addresses for the branches in the cluster. One of the determined target addresses is selected, using predicted branch directions. The selected target address is compared with a predicted target address, and resolved branch directions are compared with predicted branch directions. A misprediction is indicated if either comparison fails.

Abstract: A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.

Abstract: A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit generates local commit signals, using order information for the instruction in an issue group and any local exception signals it receives. The local commit signals are combined to generate a global commit signal for each instruction in the issue group. Local exception signals are collected at a selected one of the local exception units and processed to generate a global exception unit. The selected local exception unit resteers control of the processing resources to an exception handler associated with the global exception unit.

Abstract: A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.

Abstract: A processor pipeline includes a return stack buffer (RSB) and a top of stack pointer (RSB_TOS) to indicate the status of buffer entries. A copy of the current RSB_TOS (C_TOS) is associated with each branch instruction that is detected at the front end of the pipeline. When the branch instruction is a call instruction that is predicted taken, an associated return address is pushed onto the RSB and the current RSB_TOS is updated. When the branch instruction is a return instruction that is predicted taken, the return address indicated by the current RSB_TOS pointer is popped from the RSB and the current RSB_TOS is updated. When a branch is determined to have been mispredicted, the associated C_TOS is adjusted according to the type of branch misprediction and RSB_TOS is updated with the adjusted C_TOS.

Abstract: A system is provided for processing concurrently one or more branch instructions in an instruction bundle. The system includes multiple branch execution pipelines, each capable of executing a branch instruction to determine a branch direction, target address, and any side effects. Linking logic receives the resolved branch information and identifies a first branch instruction in execution order for which the branch direction is taken.

Abstract: A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.

Abstract: A method for gating a clock signal to an execution unit on long latency memory stalls monitors a stall signal, a scoreboard (data) hazard signal, a resource hazard signal, and a data return signal. The clock signal is decoupled from the execution unit when the stall and data hazard signals are asserted for a selected interval and the data return and resource hazard signals are not asserted for a selected interval.

Abstract: A method is disclosed for detecting overflow and underflow conditions using a status register having a main status field and first and second alternate status fields. The first and second alternate status fields are set to chop and wre modes, respectively, and chop and wre results are determined for an arithmetic operation using the first and second alternate status fields. The chop and wre results are tested against test values to determine whether an overflow or underflow condition exists.

Abstract: A method for software pipelining nested loops combines the inner and outer loops of the nested loop to form a merged loop. One or more operations from the outer loop are activated on selected passes through the merged loop, and the merged loop is software pipelined.

Abstract: A memory system for providing rapid access to cached data includes a cache, a first TLB that stores address translation entries in a truncated form for fast access to data in the cache, and a second TLB that stores full address translation entries for accurate translation. The first TLB generates the tentative physical address quickly and initiates access to the cache using the tentative physical address. A way identified using the tentative physical address is read out of the cache and compared with a validated physical address provided by the second TLB. The initiated access is allowed to complete when the tentative and validated physical addresses match.