Abstract: In accordance with one embodiment of the invention, an integrated circuit memory capable of receiving address signals has a plurality of array modules. Each array module has a plurality of memory cells arranged in rows and columns and has a means for addressing the rows and columns of the array modules in response to the address signals. The integrated memory includes a circuit for de-coupling an input address signal from array modules and for coupling of a fixed address signal to the array modules, allowing the conversion of the integrated circuit memory to a universal modular memory.