Abstract: In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stages of the pipeline system. Operation microcode is introduced for a particular stage after the templates are issued from the micromemory store but before provision thereof to the pipeline system, thereby allowing a single template to control a plurality of different operations of a particular stage within the pipeline system. Provision is also made to freeze or inhibit the issuance of subsequent templates during the execution of excessively long operations in the particular stage.

Abstract: An alignment network between N parallel data input ports and N parallel data outputs includes a first and a second barrel switch. The first barrel switch fed by the N parallel input ports shifts the N outputs thereof and in turn feeds the N-1 input data paths of the second barrel switch according to the relationship X=k.sup.y modulo N wherein x represents the output data path ordering of the first barrel switch, y represents the input data path ordering of the second barrel switch, and k equals a primitive root of the number N. The zero (0) ordered output data path of the first barrel switch is fed directly to the zero ordered output port. The N-1 output data paths of the second barrel switch are connected to the N output ports in the reverse ordering of the connections between the output data paths of the first barrel switch and the input data paths of the second barrel switch.

Abstract: In accordance with the present invention, there is provided a non-fusible web for supporting a plurality of individual solder rings in a predetermined pattern homologous with that of a plurality of solder tails or terminals on which the rings are disposed during a soldering operation. The invention finds particular application in vapor phase condensation soldering. Use of the non-fusible web provides for the simultaneous placement of a large number of individual solder rings, while eliminating the erratic and often detrimental flow characteristics occurring during the instantaneous fusion of patterned chains or strings of solder rings during a condensation soldering operation.

Abstract: The present disclosure describes electronic circuits for detecting functional failures of random access memory (RAM) devices. The circuits generate a bit pattern sequence for each memory address location and write the pattern into the memory. Subsequently, the pattern is regenerated and compared for equality with the pattern read from the memory. A complete RAM test comprises a sequence of patterns where each pattern is made to fill the entire memory matrix once. The number of test sequence patterns is a function of the bit organization of the RAM under test. Assuming that the device under test is a RAM of the type included within the tester's repertoire of testable memory devices, failure to achieve equality of the write/read patterns is indicative of a defective RAM.

Abstract: The present disclosure describes an improved side-loading wrap tool or wire wrapping bit for use on semiautomatic wiring machines. The latter are employed to make solderless wrapped connections on terminals emanating from a common plane. In contrast to the wire wrapping bits presently used on the aforementioned machines, the wrapping bit of the present invention retains the wire to be wrapped in a section of the bit which is completely separated from the terminal-receiving aperture thereof. Additionally, the configuration of the wire holding section provides a positive insulation stop and ensures the entrapment of the insulated portion of the wire within the bit in preparation for the wrap cycle.

Abstract: A modular modulo 3 module is provided having a plurality of input terminals for receiving in parallel two bytes of numerical data, and a plurality of output terminals for outputting the modulo 3 residue of each byte of data individually and the modulo 3 residue of the sum of the input bytes. The modulo 3 module is implemented through a plurality of first type modules which combine logically the numerical data on individual pairs of inputs and feed in turn a logrithmic array of second type modules which combine logically to generate the modulo 3 outputs.

Abstract: A latch assembly is described for applying a high clamping force to an electronic component installed in a suitable connector. The latch assembly insures reliable electrical connection between the component circuit leads and the connector contact elements, as well as a good ground connection between the component and a cooling frame which also serves as the system ground. The present invention finds particular application in the clamping of an interconnect cable assembly. The latter includes flat or ribbon-type cables installed in a suitable housing and adapted to be mounted in a connector. The latch is universal in that it is effective with a single full cable assembly, a pair of split assemblies or a single split assembly. Moreover the latch may be easily applied and removed without the use of tools, thereby facilitating system operations which frequently involve the removal, substitution or interchange of cable assemblies.

Abstract: A pin-shaped handheld test probe particularly adapted to current mode logic levels indicates through a plurality of visual indicators HIGH, LOW, MIDRANGE, OPEN and SUPPLY VOLTAGE logic levels. Each visual indicator is controlled by the output of at least one comparator amplifier having one of two inputs resistively connected to a testing point and the other input resistively coupled to a stable reference voltage level generated by a zener stabilized precision resistor ladder network. The testing point is voltage biased to give an indication of OPEN when the test probe is attached to a pin or point which is unconnected.

Abstract: The present disclosure describes an improved clamp for use with belted cables in the assembly of electronic equipment. In performing its clamping function, the device is adapted to engage the chassis structure upon which the cables are to be routed and terminated. The clamp design is characterized by its effectiveness with a single flat cable or a bundle of such cables. An increase in the clamping pressure exerted upon the cables results in a proportional increase in the force with which the clamp engages the chassis. This assures that the clamp will remain firmly in place during the assembly operation. Moreover, during such operation, the clamp may be easily removed to permit the addition of another cable and then reapplied. Finally, when the wiring of the cable bundle has been completed, the clamp may optionally be removed for use at another location or permitted to remain permanently in place.

Abstract: A tool is described for the holding and insertion of integrated circuit (IC) packages of the type having a metallic heat sink member fused to the chip-enclosing ceramic body. The heat sink member includes a locator or registration hole. The tool finds particular application in connection with a patented high package density island configuration wherein each IC package is secured by means of the registration hole on a retention post of a connector which is mounted between, and in close proximity to, adjacent parallel sections of the island cooling frame. The IC package heat sink member has at least one integral extension adapted to contact the frame. In performing its holding and insertion function, the tool is capable of engaging the sides of the registration hole. The assembler may then convey the IC package to the connector in which it is to be mounted, and positions the hole above the connector retention post.

Abstract: Item transport apparatus is described which finds particular application in a system for transporting and processing a variety of items or articles including mail pieces of the letter or flat variety. The processing of such items may entail the sorting, compact storing and retrieving thereof. In contrast to present day item transport apparatus in which the carrier devices themselves require an excessive volume to store the items being processed, the carrier of the invention retains the item in a sleeve of relatively thin semi-rigid material which adjusts substantially to the thickness of the item. Accordingly, depending upon the item itself, the overall thickness of the loaded carrier may be little more than that of the item and the storage efficiency is optimum.

Abstract: A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product, wherein, preferably, the multiplier multiplexor has been implemented using a modified Booth's algorithm, and wherein the column compressor operates to process every column within the same propagation delay whereby every input may create an output in essentially the same propagation time, i.e., true parallel operation requiring preferably no more than an average column propagation delay time.

Abstract: In a data processing error control system for named data, a parity check matrix and apparatus for using same provides for single error correcting of the data word and for multiple error detecting in both the data word and data name. The parity check matrix and apparatus utilize two additional parity check bits (over that required by a system using a prior art SEC/DED Hamming code) to provide protection against single bit errors, eight contiguous bit errors (i.e., hardware stuck at logical one or logical zero for the whole eight contiguous bits), similar four contiguous bit errors, and faults covering the entire data name field (which could occur, for example, if a wrong data word was fetched from memory). The parity check matrix is segmented and mated to the error correctional requirements and prevalent error modes of each field being protected. In encoding, parity check bits are generated for the combined data word and associated data name field.

Abstract: An error control system for named data functions in a hierarchical memory system environment requiring only a single error-control encoding for each data word used therein. Each level of memory in the hierarchy thereof includes a data word storage device preceded by an error checking circuit to validate and correct when possible data to be stored therein. A translator operates upon the data name of the data word to be stored to indicate the area or portion of the storage device in which the data word is to be stored. A directory table associates data names with data word locations in the storage device, and a search mechanism fed by the translator searches the directory table in the area or portion so indicated for a data word location in the storage device to store the data word. If a data word is not located in one level of memory, the next lower level of memory is searched for same.

Abstract: An alignment network having N parallel data inputs includes log.sub.2 N rounded up to the nearest integer of levels, each level therein including N selection gates for providing selectively direct through data flow and incrementally shifted or transposed data flow. The selectable shift amount in each level is equal to k.sup.2.spsp.(L-1) modulo N wherein k is relatively prime to N and is a primitive root of the rank number N, and L is the number of the level. A control signal provided to each level directs whether data flow therethrough is to be direct or transposed.

Abstract: In a microprogrammed pipelined data processing system, a template family interfacing structure sequences a plurality of templates to the pipelined system for control thereof, each template therein comprising a set of microinstructions for controlling each stage in the pipelined system. The templates are stored in a template micromemory system addressed by an address register and read to a control register. Parameters, grouped into template "Families", of the next template to be used and family parameters of the current template in use are utilized in conjunction to control the initiation of the next template to avoid conflict in any stage in the pipelined system.

Abstract: In a network for transferring a source field in a source word into a destination field in a destination word two basic hardware sub-functions are utilized: rotation and mask vector generation. In the network the destination field of a destination word is masked. Concurrently in the network, a source word is rotated bringing the source field thereof into corresponding alignment with the masked destination field and all but the source field of the source word is masked. Subsequent logical combining of the masked destination word and the rotated and masked source word generates the desired field transference. In one embodiment the required masking operation is accomplished during a single pass of the destination and source words through the network. In an alternate embodiment using less masking hardware only half of the required masking is accomplished during each pass and two passes are required before the logical combining to achieve the desired field transference.

Abstract: A single instruction multiple data (SIMD) processor particularly suited for scientific applications includes a high level language programmable front end processor, a parallel task processor having an array memory, a large very high speed secondary storage system having high speed I/O channels to the front end processor and the array memory, and a control unit directing the parallel task processor via a template control mechanism. In operation an entire task is transferred from the front end processor to the secondary storage system whereupon the task is executed on the parallel task processor under the control of the control unit thereby freeing the front end processor to perform general purpose I/O, and other tasks. Upon parallel task completion, the complete results thereof are transferred back to the front end processor from the secondary storage system. The array memory is associated with an alignment network for non-conflictingly storing and accessing linear vectors.

Abstract: A microprogrammable data communications preprocessor exercises detailed control over a multiplicity of data lines communicating with a microprogrammable central processor while requiring central processor attention on a message basis only. Further minimization of central processor intervention is achieved through a direct memory access channel which permits data transfer directly from the preprocessor to the main memory of the central processor. The preprocessor also includes a line adapter associated with each data communications line for interface purposes, a scratch pad memory for storing data line parameters, and a microprogrammable serial byte microprocessor. Operational speed is enhanced through the inclusion of automatic operation logic which effectively by-passes the serial byte microprocessor for an automatic transfer of two bytes of data.

Abstract: An arithmetic processor includes an input buffer and a result buffer connected through a pair of multiplexers to a pair of working registers feeding three parallel execution units. Operands stored in the buffers are selected for processing by addressing the buffers and multiplexers. Instruction overlapping is provided whereby operands of one instruction are read in parallel with the execution of the previous instruction. Further, reverse operations are processed identically as forward or normal operations except for addressing thereby achieving invarience of performance under non-communicative instructions.