Abstract: A power controller for selectively coupling the voltage from a primary power source to a power output terminal or coupling the voltage from a battery backup input terminal to the power output terminal includes circuitry for receiving a reset or isolation signal. After receipt of the isolation signal when the primary power source is above a first threshold voltage, the primary power source and the backup battery source will be isolated from the output power terminal on the next occurrence of the removal of the voltage from the primary power source.

Abstract: An embedded framing bit pattern in a serial bit stream is located using a sliding compare circuit to determine as each bit of the serial bit stream is received if a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the framing bit pattern match part of the framing bit pattern. A candidate register containing one plus the number of bits between each framing bit is initially preset so that all of the bits are at a first logic state and is sequentially addressed as each bit of the serial bit stream is received. If a match does not occur, then the bit addressed in the candidate register is set to a second logic state, but is not disturbed if a match occurs. The framing bit pattern has been located when the candidate register is addressing the only bit position which is still at the first logic state.

Abstract: A battery charging protection circuit for use in a power controller circuit utilizes the base emitter junction of a first NPN bipolar transistor to permit current to flow only from a backup battery input terminal to a power supply voltage output terminal of the power controller circuit. The base emitter junction and base collector junction of a second bipolar transistor are used to permit current to flow only in the direction from the backup battery input terminal to the substrate of the power controller circuit.

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted.

Abstract: An input-voltage detector circuit for increasing the functionality of a CMOS integrated circuit without requiring an increase in the number of pins or terminals of the integrated circuit includes an N-channel enhancement-mode transistor having its source terminal and substrate region electrically connected to the input of the circuit. A ground-voltage potential is applied to the gate terminal of the N-channel enhancement-mode transistor and a load element is connected between the drain terminal of the N-channel enhancement-mode transistor and the positive-voltage power supply node of the circuit. The drain terminal of the N-channel enhancement-mode transistor is further connected to a buffer stage which provides the output of the circuit. The input-voltage detector circuit detects when a voltage more negative than ground by a predetermined level is applied to the input of the detector circuit.