Abstract: A method and apparatus for placement into a programmable gate array of input-output (I/O) design objects having different voltage standards. The programmable gate array has a plurality of sites arranged into banks supporting interfaces with a plurality of different input and output voltage standards. In an example embodiment, I/O design objects are placed into IOBs of the programmable gate array by first performing simulated annealing that considers conflicts between design object voltage standards as placed into the IOBs. Then, a bipartite matching is performed using placement results from simulated annealing. Finally, if the bipartite matching does not produce a feasible placement, standards are assigned to the banks based on the previous placement results, and the bipartite matching process is repeated.
Type:
Grant
Filed:
June 29, 1998
Date of Patent:
September 11, 2001
Assignee:
Xilinx, Inc.
Inventors:
Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Sudip K. Nag, Rajeev Jayaraman