Abstract: Generation a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a first partial remainder, which has a fixed width greater than or equal to the width of the second polynomial, from the first polynomial excepting a least significant portion. The first adder is adapted to generate a sum of the least significant portion of the first polynomial and a most significant portion of the first partial remainder. The second sub-circuit is adapted to generate a second partial remainder from the sum. The second adder is adapted to generate the remainder from the second partial remainder and the first partial remainder excepting the most significant portion.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

Abstract: A cost efficient nonvolatile memory cell may include an inverter, an access gate coupled to the inverter for controlling access to the memory cell, and a control gate. The inverter may include a floating gate at an input of the inverter, the floating gate formed in a first polysilicon layer, and a tunnel window formed in a tunnel oxide area, wherein the tunnel oxide area is covered by at least a portion of the floating gate. The control gate may control charge on the floating gate, and may be formed in a second polysilicon layer, wherein the second polysilicon layer is above the first polysilicon layer.

Abstract: A cache management method in a cache system having a plurality of processors for managing the cache storage. Each of the processors may reserve portions of the cache storage which future allocation of cache storage may be expedited. All the processors begin searching for a portion of cache storage to allocate with the same starting portion of cache storage when processing cache commands in which the referenced data is not present in the cache storage. A processor will advance past the starting portion of cache storage when allocation of a portion of cache storage is necessary and another processor is currently using the starting portion of cache storage.