Abstract: A system is provided for terminating processes that are executing on a plurality of distributed computing nodes. The system comprises a batch queuing system configured to receive jobs from a user and to dispatch jobs to the distributed computing nodes. A process shutdown interface is included that is configured to receive task criteria for terminating processes corresponding to the task criteria on the distributed computing nodes. An automatic process shutdown module is in communication with the process shutdown interface. The automatic process shutdown module is configured to retrieve information based on the task criteria from the batch queuing system regarding the processing location of jobs submitted to the batch queuing system. The automatic process shutdown module is also configured to terminate the processes on the computing nodes for jobs that are identified using the information obtained from the batch queuing system.

Abstract: Image capture device control marks are automatically generated within a computer or printer and automatically printed on pages output from the printer. The control marks when detected by a control mark capable image capture device communicate information to the image capture device such as which areas of the printed page are text that require optical character recognition, which areas of the page are photos that require high-resolution full-color, which areas of the page are line drawings that require medium-resolution black and white, and which areas of the page are not to be scanned. Image capture device control marks may be configured in a wide range of sizes, styles, and locations on the printed page.

Abstract: A printed circuit board is built including metal traces for a differential clock. Within a break in each metal trace pads for a delay line socket are included along with pads for two 0-ohm resistors in series. In between the two 0-ohm resistors metal traces are build in a configuration to provide a specified delay in a signal passing through the trace. This group of pads and traces allows a designer to test (on the completed printed circuit board) differential clocks in modes including negative skew. In normal operation, the 0-ohm resistors are present on the printed circuit board and the clock signals pass through the metal traces build in a configuration to provide a specified delay in the signals passing through the traces. During testing, delay lines may be placed in the delay line sockets and the 0-ohm resistors may be removed.

Abstract: A thermal interface pad is constructed from a plurality of thermal interface plate assemblies. Alternate thermal interface plate assemblies are rotated about 180 degrees from each other within the pad. Each plate assembly includes one or more spring members configured such that the completed thermal interface pad includes a plurality of spring members on at least two sides of the pad. The thermal interface plate assemblies are configured to allow the thermal interface pad to vary greatly in thickness. The pad is sufficiently adjustable in thickness to accommodate gross tolerance differences between multiple heat generating and sinking devices. Rods inserted in openings in the plates may be used to align the plate assemblies and to apply compressive force to the plates, improving the thermal conductivity between adjacent plates and greatly decreasing the overall thermal resistance of the thermal interface pad.

Abstract: A first heat sink is built including two sets of fins with a gap between the two fin sets. The gap is configured to allow the placement of a second heat sink between the two fin sets of the first heat sink. The first heat sink also includes slotted mounting lugs to allow the second heat sink to be mounted to the first heat sink allowing for varying stack up tolerances of the heat generating devices cooled by the first and second heat sinks.

Abstract: A heat sink is constructed including at least one heat sink fin. Each fin includes an opening sized to fit a thermal device when the fins are heated to a temperature above that of the thermal device. When the fins cool to the temperature of the thermal device they shrink in size and form a tight compression fit around the thermal device.

Abstract: A heat sink is built including a three dimensional array of cylindrical openings for air to flow through instead of fins. By having a larger surface area than heat sinks with fins, this high surface area heat sink results in increased heat transfer to the surrounding air than a similarly sized heat sink with fins. Heat sinks including an array of cylindrical openings may be manufactured through extrusion, stamping, and other common techniques.

Abstract: An image without use of a flash is taken, along with an image using a flash. A difference image is generated by subtracting the flash-less image from the flash image. A threshold is applied to the difference image such that only large differences in intensity remain in the difference image. This artifact image is then subtracted from the flash image, thereby removing flash artifacts such as specular reflections and red-eye. The threshold used may be automatically calculated or may be set by the user. For some applications it may be desirable to set separate thresholds for each dimension of the color space (such as red, green, and blue) used. Once again these separate thresholds may be automatically calculated or may be set by the user.

Abstract: A circuit module including at least one Application Specific Integrated Circuit (ASIC) and a plurality of Vertical Cavity Surface-Emitting Laser (VCSEL) array modules is built using a standard ceramic or organic VLSI package substrate, resulting is a high density device with a small footprint. Interconnection between the electronic devices and the VCSEL array modules is accomplished using standard integrated circuit packaging technology and flexible connectors. Optical connections from the VCSEL arrays to fiber optic cables are made possible by integrating industry-standard optical connectors onto the package. Optical receiver and transceiver modules may also be incorporated into the circuit module.

Abstract: A first printed circuit board is built including one or more openings configured to correspond to heat-generating devices attached to a second printed circuit board. The first and second printed circuit boards are aligned with each other and a heat sink, such that the heat sink is thermally coupled with heat-generating electronic devices on both the first and second printed circuit boards. Optionally, the first and second printed circuit boards may be electrically coupled with each other through an electrical connector. Also optionally, heat-generating devices may be mechanically and electrically coupled with the second printed circuit board through interposers configured (upon assembly) to raise the heat-generating devices through the openings in the first printed circuit board to contact a heat sink.

Abstract: A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

Abstract: A first printed circuit board is built including one or more openings configured to correspond to heat-generating devices attached to a second printed circuit board. The first and second printed circuit boards are aligned with each other and a heat sink, such that the heat sink is thermally coupled with heat-generating electronic devices on both the first and second printed circuit boards. Heat-generating devices are thermally coupled with a thermal pad on one or more of the printed circuit boards. The thermal pad is then thermally coupled with the heat sink. Optionally, the first and second printed circuit boards may be electrically coupled with each other through an electrical connector.

Abstract: An electronic device is built including a memory, a processor, and a display. The processor is configured to calculate an array of estimated travel time data from a first location to a plurality of locations within a destination area from a set of situational parameters and a set of user parameters. These situational parameters may include data such as: the location, condition, and speed limits of roads and paths; the availability of public transportation; terrain information such as elevation, slope, the presence of trails and vegetation; and weather information such as wind speed and precipitation. User parameters may include data such as: the user's mode of transportation, the user's physical abilities, and the load the user is carrying.

Abstract: A first printed circuit board is built including one or more openings configured to correspond to heat-generating devices attached to a second printed circuit board. The first and second printed circuit boards are aligned with each other and a heat sink, such that the heat sink is thermally coupled with heat-generating electronic devices on both the first and second printed circuit boards. Heat-generating devices are thermally coupled with a thermal pad on one or more of the printed circuit boards. The thermal pad is then thermally coupled with the heat sink. Optionally, the first and second printed circuit boards may be electrically coupled with each other through an electrical connector.

Abstract: A circuit module including at least one Application Specific Integrated Circuit (ASIC) and a plurality of Vertical Cavity Surface-Emitting Laser (VCSEL) array modules is built using a standard ceramic or organic Multi-Chip Module (MCM) package substrate, resulting is a high density device with a small footprint. Interconnection between the electronic devices and the VCSEL array modules is accomplished using standard integrated circuit packaging technology and flexible connectors. Optical connections from the VCSEL arrays to fiber optic cables are made possible by integrating industry-standard optical connectors onto the package. Optical receiver and transceiver modules may also be incorporated into the circuit module.

Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.

Abstract: A thermal interface pad is constructed from a plurality of thermal interface plate assemblies. Alternate thermal interface plate assemblies are rotated about 180 degrees from each other within the pad. Each plate assembly includes one or more spring members configured such that the completed thermal interface pad includes a plurality of spring members on at least two sides of the pad. The thermal interface plate assemblies are configured to allow the thermal interface pad to vary greatly in thickness. The pad is sufficiently adjustable in thickness to accommodate gross tolerance differences between multiple heat generating and sinking devices. Rods inserted in openings in the plates may be used to align the plate assemblies and to apply compressive force to the plates, improving the thermal conductivity between adjacent plates and greatly decreasing the overall thermal resistance of the thermal interface pad.

Abstract: A first printed circuit board is built including one or more openings configured to correspond to heat-generating devices attached to a second printed circuit board. The first and second printed circuit boards are aligned with each other and a heat sink, such that the heat sink is thermally coupled with heat-generating electronic devices on both the first and second printed circuit boards. Heat-generating devices are thermally coupled with a thermal pad on one or more of the printed circuit boards. The thermal pad is then thermally coupled with the heat sink. Optionally, the first and second printed circuit boards may be electrically coupled with each other through an electrical connector.

Abstract: A first printed circuit board is built including one or more openings configured to correspond to heat-generating devices attached to a second printed circuit board. The first and second printed circuit boards are aligned with each other and a heat sink, such that the heat sink is thermally coupled with heat-generating electronic devices on both the first and second printed circuit boards. Heat-generating devices are thermally coupled with a thermal pad on one or more of the printed circuit boards. The thermal pad is then thermally coupled with the heat sink. Optionally, the first and second printed circuit boards may be electrically coupled with each other through an electrical connector.

Abstract: An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.