Abstract: A process for treating silica dielectric film on a substrate, which includes reacting a suitable hydrophilic silica film with an effective amount of a multifunctional surface modification agent. The film is present on a substrate and optionally has a pore structure with hydrophilic pore surfaces, and the reaction is conducted for a period of time sufficient for said surface modification agent to penetrate said pore structure and produce a treated silica film having a dielectric constant of about 3 or less, wherein the surface modification agent is hydrophobic and suitable for silylating or capping silanol moieties on such hydrophilic surfaces. Dielectric films and integrated circuits including such films are also disclosed.

Abstract: The present invention relates to novel low dielectric constant nanoporous dielectric films having improved mechanical strength, and to improved processes for producing the same on substrates suitable for use in the production of integrated circuits. The nanoporous dielectric films are prepared by a process of preparing a mixture of a spin-on-glass material with a suitable thermally degradable polymer that is soluble in polar solvents. The resulting mixture is then applied onto a substrate suitable for use in the production of an integrated circuit, to produce a coated substrate that is heated for a time and at one or more temperatures effective to degrade the polymer, so as to produce the desired low dielectric nanoporous dielectric film.

Abstract: A method for cleaning the surface of a semiconductor wafer having an organic dielectric film thereon by removing residual slurry particles adhered to the wafer surface after chemical-mechanical planarization is provided. The semiconductor is subjected to a post CMP cleaning step by applying mechanical frictional force to the surface of the wafer while concurrently applying to the wafer surface and aqueous solution having a pH of greater than 10 for a period of time sufficient to wet and clean the wafer surface, the basic aqueous solution comprised of a surfactant and a tetra alkyl quaternary ammonium hydroxide compound such as tetramethylammonium hydroxide.

Abstract: A method for forming a gap-filled, planarization structure of dielectric materials on a substrate topography useful for forming microelectronic devices. A dielectric material is first deposited as continuous, dry dielectric layer, preferably a SOG layer. Then the dielectric layer is partially removed by chemical-mechanical polishing (CMP). The chemical and mechanical properties of the structure can be chosen by varying the composition of the SOG layer and the subsequent CMP conditions.

Abstract: A method for purging and passivating a vacuum chamber suitable for use in the production of integrated circuit structures on semiconductor wafers. The method includes flowing a heated, non-reactive gas, such as argon gas, through the chamber for purposes of decontaminating the chamber and subsequently filling the chamber with a selected gas such as nitrogen to passivate the chamber for storage or shipping purposes.

Abstract: An apparatus for polishing semiconductor wafers and other workpieces that includes polishing pads mounted on respective platens at multiple polishing stations. Multiple wafer heads, at least one greater in number than the number of polishing stations, can be loaded with individual wafers. The wafer heads are suspended from a carousel, which provides circumferential positioning of the heads relative to the polishing pads, and the wafer heads oscillate radially as supported by the carousel to sweep linearly across the respective pads in radial directions with respect to the rotatable carousel. Each polishing station includes a pad conditioner to recondition the polishing pad so that it retains a high polishing rate. Washing stations may be disposed between polishing stations and between the polishing stations and a transfer and washing station to wash the wafer as the carousel moves. A transfer and washing station is disposed similarly to the polishing pads.

Abstract: An improved slit valve door for sealing an aperture in the wall of a semiconductor process chamber. The slit valve door consists of an aperture cover plate with a recess in it for receiving a removable insert. An O-ring seal is placed over the insert, and when the insert is placed in the recess of the aperture cover plate, the O-ring moves into an O-ring seat in the aperture cover plate. As the insert seats in the recess and is secured to the cover plate by means of screws protruding from the floor of the recess, a dovetail groove is formed which retains the O-ring.