Abstract: An FPGA architecture and method to reduce the size of the bitstream used in configuring or reconfiguring the FPGA. To facilitate features of the compression process, an FPGA is modified to implement an addressable data register in place of a conventional shift register. This allows data frames to be arranged in order of similarity, and a bitstream formed from one full data frame along with an address into which the frame is to be loaded, and subsequent partial data frames including only changed words along with the row address of the changes and the column address into which modified frames are to be loaded, rather than shifting in entire frames of data for subsequent frames.

Abstract: A survival and training apparatus for children is constructed in the form of a teddy bear. The teddy bear has an exterior casing formed of multiple durable materials including a fluorescent fabric of lime yellow color that is visible during daytime conditions and a reflective fabric to facilitate visibility during nighttime conditions. A third fabric which stores light energy during the day and then emits it at night can also be included in the casing materials. The teddy bear also includes in interior filling material of polystyrene beads that facilitates human body heat insulation when the survival teddy bear is held by the child and imparts buoyancy to enable the survival teddy bear to operate as a floatation device. The survival apparatus hits a pocket formed in the back to receive and warm a child's hands. A whistle is attached via a chord to the pocket and can be alternatively inserted into the pocket for storage and retrieved therefrom for use by the child.