Abstract: A multiprocessor computer system having a first processor having a first interrupt mechanism for generating interrupt requests, a second processor having a second interrupt mechanism, and a system bus for communicating interrupt requests from the first processor to the second processor. The second interrupt mechanism is responsive to an interrupt request by generating an acknowledge response on the system bus when the second processor accepts the interrupt request and generating a not acknowledge response on the system bus when the second processor contains a previous and pending interrupt request of higher level and refuses the interrupt request. The second interrupt mechanism is responsive to the completion of servicing of an interrupt request by the second processor by placing on the system bus an interrupt completed command, which includes an address identifying the second processor and a code indicating that the second processor has completing servicing an interrupt request.

Abstract: A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

Abstract: A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability.

Abstract: A method of searching the directory of a database, held in the store of an information processing system, to identify an entry in the directory which most closely matches a search entry, each of said directory entries containing first, second and third fields, said search entry containing at least a first field, and each of said fields having the capability of including multiple parts: wherein the set of all directory entries which have the first part of the first field thereof the same as the first part of the first field of the search entry are retrieved from the directory; wherein all parts of the first field of each entry of said set are compared with a similar number of parts of the search entry and according to the degree of match of such comparison, a respective value is calculated for such degree of match; wherein similar comparisons are made between the second and third fields, if any, of each entry of the set and the search entry; and wherein the highest of such calculated values indicates the direc

Abstract: A queue manager for controlling the execution of requests for the transport of messages from users to destinations. Each request includes a message and an identification of a destination. The queue manager includes a queue for storing pending requests and a dispatcher task for creating a worker task to execute each request and provides a method for adapting the execution of requests to constraints and characteristics of destinations and communications links.

Abstract: A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

Abstract: In a distributed data system in which processes running in trusted systems whose results may be proprietary or sensitive in nature may be invoked by operators at remote, untrusted workstations, and in which said processes are provided with locks which do not permit proprietary or sensitive actions unless a request includes a key matching the lock, a method of associating keys with operators is based on each operator's presenting his ID and a valid password at the workstation at the time he logs on to the system, verifying his password in a trusted system, correlating his ID with a role or group of roles he is authorized to fulfill, and retrieving and storing in the memory of the trusted system, associated with the operator's ID, a list of keys (a "keyring") for each of those roles. The operator's ID is appended to every request he invokes, a process containing a lock interrogates the stored list and will not grant a proprietary action unless the stored list contains a key matching the lock.

Abstract: A prefix index tree structure for locating data records stored through keys related to information stored in data records. Each node includes a prefix field for a prefix string of length p of the longest string of key characters shared by all subtrees of the node and a data record field for a reference to a data record whose key is completed by the prefix string. A node may include one or more branch fields when the prefix string is a prefix of keys stored in at least one subtree of the node, with a branch field for each distinct p+1.sup.st key character in the keys, wherein each p+1.sup.st key character is a branch character. Each branch field includes a branch character and a branch pointer field for a reference to a node containing at least one key whose p+1.sup.st character is the branch character. Each node further includes a field for storing the number of key characters in the prefix string and a field for storing the number of branch fields in the node.

Abstract: In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

Abstract: A bus interface interrupt arrangement is disclosed which provides separate interrupt controllers for each bus in a multibus computer system where the processor is connected to one of the busses. Interrupt requests decided on each of the busses other than a primary bus to which the processor is connected are input along with interrupts from circuits connected to the primary bus to the interrupt controller for the primary bus. The interrupt request decided by the interrupt controller for the primary bus is connected to an interrupt input of the processor. All interrupt controllers are connected to the primary bus and may be accessed by the processor. When an interrupt from one of the busses other than the primary bus is chosen by the processor, the processor must read the interrupt controllers to determine first what bus, and then identify the circuit that generated the interrupt that has been acknowledged.

Abstract: During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.

Abstract: Timing unit for generating a timing signal for synchronous microprocessors in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor. A frequency divider divides the base frequency by four, and a shift register clocked by the base frequency and receiving a timing signal from the frequency divider, generates a mask signal. The mask signal is selectively applied to a control input of the frequency divider in response to one or more control signals, to inhibit the switching of the frequency divider. This thereby introduces in the phases of the timing frequency, wait states equal to 1/4 (or multiple thereof) of the timing frequency, thereby matching the microprocessor speed to the memory read/write cycle time.

Abstract: A communication data system is designed for resiliency by automatically replacing or bypassing defective units. The system includes a number of input/output terminals which are connected to MODEMs through a relay bank. The MODEMs send serial data to a serial I/O module which converts the serial data to bytes which it places on a VMEbus. A network processor sends the data from the VMEbus to a general purpose computer which places the data into the communications network. A general purpose computer or a back-up general purpose computer may detect a defective communication link and automatically switch to a back-up network computer, or cause a control module to switch the relay module to a spare MODEM and spare SIO. The control module may also generate a remote line test to the link between the MODEM and the terminal to determine if that link is defective.

Abstract: The apparatus provides a secure input/output command system by the operating system generating a virtual input/output command including a virtual channel number, verifying that the user has authorization to access the processes and the device, and then generating a physical input/output command for transfer over a system bus to the device addressed by the physical channel number included in the command.

Abstract: Arbitration circuit operates for common bus access granting where the asynchronous access requests are latched in a register by the rising edge of a periodical square wave timing signal, and from there transferred to a logical priority network, implemented with a programmable logic array.

Abstract: A multiprocessor system includes a number of subsystems all coupled in common to an asynchronous system bus. Apparatus is included in the system bus interface logic of each processing subsystem to receive commands from the system bus and compare the interrupt priority level of the new command with the current command being executed. If the new command has a lower interrupt priority than the current command, then the subsystem sending the command will receive a not acknowledge response from the processing system. The apparatus is responsive to certain control signals from the new command to bypass the interrupt priority comparison logic and initiate an immediate interrupt regardless of the interrupt priority level of the current command being executed by the processing subsystem. The processing subsystem may also generate a command to itself via the system bus which requires the high speed interrupt.

Abstract: An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.

Abstract: A host computer stores data and attribute bytes for display on a terminal or personal computer having a monochrome screen. The monochrome attributes include low intensity, underline, inverse, blink and hide. The host computer may communicate with a terminal or personal computer having a color screen without modifying the host program or the data and attribute bytes. The terminal or personal computer operator may determine the color and attribute for each of the monochrome attributes.

Abstract: Power recovery circuit for printer haivng printing elements actuated by electromagnets energized by a voltage VS available at a terminal. The circuit includes a voltage booster for generating a voltage HV higher than voltage VS at a node and a buffer capacitor charged by the voltage HV and connected between the terminal and the node, a connection between the electromagnets and the node for transferring the magnetic energy imparted to the electromagnets by the buffer capacitor for storing therein as capacitive energy, an inductor and a control switch, series connected between the node and the terminal, a recirculation diode connected between ground and the node common to the switch and the inductor, a voltage detector providing an enabling signal when voltage HV exceeds a predetermined level and a controlled oscillator, enabled by the enabling signal to generate a control signal which periodically switches the control switch on and off.

Abstract: A computer network system for multiple processing elements in which the multiple processing elements are coupled to a single network bus such that computer instructions from the processing elements may be transimtted simultaneously over the same network during one time interval by more than one processing element. A memory stores the instructions and a controller accepts instructions from one of the processing elements but rejects instructions from all other elements and stores and queues the rejected instructions for subsequent acceptance.