Abstract: A wire serves as a gettering material which is wire-bonded to electrical connections which lead outside of a vacuum sealed package. The wire can be activated to create and maintain a high integrity vacuum environment. The "getter" can be either heat activated or evaporated by the passing of an AC or DC current through the wire.

Abstract: A method is provided for forming inter-electrode spacers useful in flat panel display devices which comprises placing a mold on a first electrode plate. The mold has openings with corresponding diameters. The mold is coated with a conformal film which lines the openings, thereby decreasing the diameters of the openings. The openings are filled with a glass material. The conformal film is selectively removed, and the mold is separated from the electrode.

Abstract: A process is provided for forming spacers useful in large area displays. The process comprises steps of: forming bundles comprising fiber strands which are held together with a binder; slicing the bundles into slices; adhering the slices on an electrode plate of the display; and removing the binder.

Abstract: Another aspect of the present invention comprises a method for fabricating columnar supports used for an evacuated display, in which an electrode plate is covered with a layer of material having a depth. The material is used to form the columnar supports, and the depth of the layer represents the height of the columnar supports. The material is selectively irradiated with light energy in a pattern causing the material to harden, thereby forming the columnar supports.

Abstract: A method for etching structures having topography, which structures are comprised of polysilicon disposed over an oxide, by placing an electrostatic shield on a high density source etcher while etching the structures. The etch involves the removal of the polysilicon which overhangs the oxide structure below it, thereby substantially eliminating conductive stringers.

Abstract: The present invention teaches a method for fabricating an ultrathin uniform dielectric layer over a silicon or polysilicon semiconductor substrate. The method entails first providing a substrate having a conductive area into a chamber. Subsequently, the first conductive material is destabilized by introducing it to reactive gas and radiant energy in situ. The reactive gas can be Ar-H.sub.2, H.sub.2, GeH.sub.4 or NF.sub.3 gas. The radiant energy source can be ultraviolet ("UV") or Tungsten Halogen lamps preferably having an approximate range of 0.2 to 1.6 .mu.m to provide heat of approximately 850.degree. to 1150.degree. C. for approximately 10 to 60 seconds at a vacuum pressure range of 10.sup.-10 Torr to atmospheric pressure. This process removes the native oxide and breaks the molecular clusters present on the silicon or polysilicon surface. Thereafter, a first dielectric layer having a substantially uniform thickness forms directly above the substrate by the in situ introduction of NH.sub.

Abstract: A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: A method for removing carbon-based polymer residues to effect a cleaning of a reactor, such as a planar plasma reactor, by exciting an ozone containing atmosphere in the reactor, which atmosphere is reactive with the carbon-based residues thereby forming volatile end products, which end products can be evacuated from the reactor.

Abstract: A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material removed through the sputter etch process is oxidized and redeposited along the sides of the feature and along the surface of the substrate, thereby improving step coverage when a subsequent dielectric layer is deposited thereon.

Abstract: A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 .ANG.. A barrier layer is then formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer is preferably Si.sub.3 N.sub.4. A glass layer is then formed superjacent the barrier layer. The glass layer has a thickness of at least 1 k.ANG.. The glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for 5 to 60 seconds, thereby making said glass layer planar. The radiant energy generates a temperature within the range of 700.degree. C. to 1250.degree. C. Further, the gas is at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar-H.sub.2, H.sub.

Abstract: A process useful for isolating active areas of semiconductor devices, comprising the steps of: forming pad oxide, polysilicon, and nitride layers superjacent a substrate; patterning and etching the layers and the substrate, thereby forming a recess in the substrate; forming a nitride spacer within the recess, then growing a field oxide region therein; removing the layers thereby causing an indentation to form within the periphery of the field oxide region; disposing polysilicon within the indentation; etching the polysilicon to a level even with the field oxide region; and oxidizing the polysilicon.

Abstract: A method for forming a substantially uniform array of atomically sharp emitter tips, comprising: patterning a substrate with a mask, thereby defining an array; isotropically etching the array to form pointed tips; and removing the mask when substantially all of the tips have become sharp. A mask having a composition and dimensions which enable the mask to remain balanced on the apex of the tips until all of the tips are of substantially the same shape is used to form the array of substantially uniform tips.

Abstract: A cleaner, selective etch process wherein NF.sub.3 ions and nitrogen ions are employed to bombard a patterned nitride layer disposed superjacent an oxide layer, thereby creating substantially vertical sidewalls, especially useful when etching submicron features.

Abstract: A method is disclosed for reducing the effects of semiconductor deformities. Initially, a semiconductor substrate is provided. The substrate has at least one layer superjacent the substrate and at least one layer subjacent the substrate. Subsequently, the semiconductor structure is examined for warp and bow type deformities. As a result of this examination, the warp and bow measurements of the semiconductor structure are compared with a reference. In the event that the measured warp and bow exceed a predetermined tolerance, either the thickness of the layer superjacent or the thickness of the layer subjacent is reduced. This reducing step can be accomplished by chemical and/or mechanical planarization, dry etching, wet etching or plasma etching.

Abstract: The process of the present invention comprises the addition of an adequate amount of argon gas in a dry etch system to clear bond pads of residual contaminants which form an undesired oxide coating on the bond pads. Carbon dioxide may be used as a carrier gas along with the argon gas. The process of the present invention preferably takes place in situ, following the silicon nitride pad etch in which fluorine-containing chemicals are used to form the bond pads.

Abstract: A semiconductor wafer is washed in a dilute phosphoric acid solution after the metal features have been patterned and etched, thereby removing substantially all of the residual oxide, chlorine, and/or fluorine contamination which remains on the features. This will substantially eliminate corrosion of the features. The phosphoric acid wash also substantially prevents voids from forming during a subsequent alloy step. The features can include bond pads, vias, contacts, interconnects, etc.

Abstract: A method for fabricating semiconductor wafers is disclosed, wherein a semiconductor substrate is provided in a chamber. Subsequently, a first silicon nitride layer is formed in situ under high pressure superjacent the substrate by introducing a gas containing nitrogen, preferably NH.sub.3 combined with N.sub.2, at a temperature within the range of 850.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds. This results in the first layer having a thickness in the approximate range of 5 .ANG. to 30 .ANG.. A semiconductor film is then deposited in situ under high pressure superjacent the first silicon nitride layer, preferably by means of Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). In an alternate embodiment of the present invention, this is accomplished by either Low Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy ("MBE"). The thickness of the film is in the approximate range of 10 .ANG. to 40 .ANG..

Abstract: A field emitter structure is formed, having trench accessible cold cathode tips is fabricated by forming trenches in a substrate. The trenches are subsequently filled with a conformal insulating layer, a highly conductive layer, and a polysilicon layer. The layers are etched to form emitter tips which are disposed contiguous with the trenches. Electrical signals are propagated through the trenches permitting increased performance of the emitter structure.

Abstract: A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.