Abstract: Briefly, in accordance with one embodiment of the invention, a platform bus interface unit includes circuitry to divide a received network protocol compliant signal packet into signal packets of a smaller size for transmission over a platform bus of at least a portion of the data provided by the network protocol compliant signal packet.
Briefly, in accordance with another embodiment of the invention, an integrated circuit includes circuitry to transmit over a platform bus at least a portion of the data provided by a network protocol compliant signal packet as signal packets of a smaller size.
Briefly, in accordance with still another embodiment of the invention, a method of transmitting at least a portion of the data provided by a network protocol compliant signal packet over a platform bus includes the following. At least a portion of the data provided by the network protocol compliant signal packet is divided into smaller data subsets.
Abstract: A method, apparatus, and system are described for rasterizing a triangle. Pixel parameter values are interpolated by adding or subtracting a vertical delta and/or by adding or subtracting a horizontal delta within a 4×4 tile of 16 pixels.
Abstract: A method for verifying the integrity of a media key block (MKB) by storing validation data in a validation area of a medium, such as a DVD-R or a DVD-RW. In one embodiment, validation data comprises a hash function on a media key block. In another embodiment, validation data comprises the Verification Data field of an MKB's Verify Media Key Record.
Type:
Grant
Filed:
March 30, 2001
Date of Patent:
May 18, 2004
Assignees:
Intel Corporation, International Business Machines Corporation, Toshiba Corporation, Matsushita Electric Industrial Co., Ltd.
Inventors:
Michael S. Ripley, Jeffrey B. Lotspiech, Atsushi Ishihara, Taku Kato, Yoshihisa Fukushima
Abstract: A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (“MCH”). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conserving power consumption.