Abstract: A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first performs a zero detect on each byte of data retrieved from memory. The zero detect results are next decoded according to bit selection signals generated from a data format code which corresponds to the specific format of the retrieved data.

Abstract: A computer game controller system and method has a pulse position modulated (PPM) input device for encoding status information in a pulse position control signal and a bimodal interface having a first and second interface circuits, each for coupling an input device to a computer game program. The first interface circuit is a pulse position signal decoder for decoding a pulse position control signal. The second interface circuit is a capacitor charge decoding circuit for decoding a variable resistance input compatible with the IBM game port standard. When the bimodal interface is coupled to a PPM input device, the received pulse position control signal is decoded with improved accuracy and speed using the first interface (the PPM decoder). However, when the bimodal interface is coupled to a conventional input device which generates a variable resistance input conforming to the IBM game port standard, the second interface (the capacitor charging network) is used to decode the control signal.

Abstract: A digital, radio-frequency (RF) transceiver is modified by coupling an infra-red (IR) communication subsystem thereto. The subsystem includes an IR transmitter and receiver which may be coupled selectably by a switch to a data signal channel or source in the transceiver. Preferably, the IR receiver includes an inductor and a diode coupled in parallel, such that the IR receiver detects an IR signal, in significant part, by resonating such signal substantially at a detection or RF baseband frequency.

Abstract: An expandable data processing chassis and method of assembly of an expandable data processing chassis includes stackable circuit board housings and a central circuit board housing. The stackable circuit board housings and the central housing each have a rigid interlockable stabilizing frame plate to maintain mechanical tolerances as stackable circuit board housings are added to the stack. Each of the circuit board housings also has an associated backplane for coupling the circuit boards received in each housing to each other and to the central housing. The backplanes also extend to a power backplane for supplying power to the circuit boards received in the expandable data processing chassis.