Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Abstract: Methods of etching a semiconductor structure using ion milling with a variable-position endpoint detector to unlayer multiple interconnect layers, including low-k dielectric films. The ion milling process is controlled for each material type to maintain a planar surface with minimal damage to the exposed materials. In so doing, an ion beam mills a first layer and detects an endpoint thereof using an optical detector positioned within the ion beam adjacent the first layer to expose a second layer of low-k dielectric film. Once the low-k dielectric film is exposed, a portion of the low-k dielectric film may be removed to provide spaces therein, which are backfilled with a material and polished to remove the backfill material and a layer of the multiple interconnect metal layers. Still further, the exposed low-k dielectric film may then be removed, and the exposed metal vias polished.

Abstract: Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

Abstract: A method for the manufacture of micro metallic structures having high aspect ratios is provided, wherein said method comprises the step of photolithographically producing trenches in a substrate. Polymer chains are formed on the inner surface of said trenches. Thus, the critical dimensions in the photolithographical process can be reduced to any dimension down to zero. The method is quite general in its application to any process that includes the definition of a critical dimension by photolithography. Immediate applications are the reduction of the read and write dimensions in thin film magnetic heads, but the invention can be used in any technology where the manufacture of microstructures having a high aspect ratio is of interest.

Abstract: An apparatus for removing attached die having a pivoting means, having a pivot point and first and second sides, the pivot point having a corresponding first y coordinate, the first and second sides positioned opposite to one another, said pivoting means capable of attaching to a die carrier. The apparatus also having a shaft attached to the first side of the pivoting means. The apparatus further having a counterweight attached to the second side of the pivoting means. The apparatus lastly having a clamping means capable of attaching to at least one die, the die having a corresponding second y coordinate, wherein the first y coordinate is greater than the second y coordinate.

Abstract: There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17?) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A?,B?) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset.

Abstract: Ink jet printing apparatus is employed to form a non-polar ink stop line around a chip site on the polar surface of an organic laminate substrate. The non-polar ink stop line acts to confine polar liquid flux from spreading after application of the flux to the chip site prior to chip joining. Excessive flux spreading results in insufficient flux being present at the chip site for the formation of good electrical connections during solder reflow upon chip joining.

Abstract: An apparatus for measuring ammonia gas concentration in an ongoing chemical mechanical polishing (CMP) cycle utilizing an acidic CMP slurry, having the following components: a. A transferring means to collect a sample of the acidic CMP slurry; b. A converting means to convert the acidic CMP slurry to a basic slurry; c. A measuring means to measure the ammonia gas present in the basic slurry; d. A detection means to signal the end of an ongoing CMP cycle.

Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.

Abstract: An apparatus for measuring ammonia gas concentration in an ongoing mechanical polishing (CMP) cycle utilizing an acidic CMP slurry, having the following components: a. A transferring means to collect a sample of the acidic CMP slurry; b. A converting means to convert the acidic CMP slurry to a basic slurry; c. A measuring means to measure the ammonia gas present in the basic slurry; d. A detection means to signal the end of an ongoing CMP cycle.

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13?) is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measurement apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not require dedicated pins and measurement apparatus. In order to measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, then a rising edge detector (405) is used to analyze logic path signals, A counter (410) based on a system clock is used to measure propagation delay.

Abstract: A reinforced semiconductor interconnect structure, having the following components: (1) A first metal interconnect disposed in a first material, the first metal interconnect having a line portion and at least one via portion, an anode section and a cathode section, the via portion of the first metal interconnect located in the anode section, the line portion of the first metal interconnect having a top, bottom and terminus side, wherein at least a part of the bottom side of the line portion of the first metal interconnect in contact with the first dielectric; and (2) a first reinforcement disposed in the first material, the first reinforcement in contact with at least the bottom side of the first metal interconnect, the first reinforcement comprising a second material, the second material being electrically nonconductive; and wherein the second material has a greater mechanical rigidity than the first material.