Abstract: A method for isolating elements in semiconductor devices is disclosed, which includes the steps of: forming a field oxide layer on the surface of a semiconductor substrate; using a photo resist pattern to define a field region and an active region; carrying out an ion implantation of several MeV with the photo resist pattern remaining on the field region, so as to form a channel stop layer on the field oxide layer region; and forming a soft error-preventing buried layer in the active region. The field insulating layer may be a silicon oxide layer or a silicon nitride layer. Additionally, a selective epitaxial process may be carried out so as to raise the level of the active region to substantially the height of the field isolating region, thereby flattening the surface.

Abstract: A sync signal separating circuit of an image output apparatus includes an inversion amplifying section for providing a green video signal supplied from a video signal generator to be output as an output signal that is inverted and amplified, and a clipper receiving the output signal of the inversion amplifying section as an input signal to output a clipped output signal obtained by cutting over or below a prescribed amplitude. Here, the inversion amplifying section has an amplifying device, an input resistor and a feedback resistor, and the clipper has a diode having an anode connected to the output side of the inversion amplifying section and a load resistor having one side connected to a cathode of the diode and the other side grounded. Thus, the sync signal is accurately produced from the cathode of the diode without requiring a conventional horizontal sync signal detecting section.

Abstract: An EEPROM flash memory cell and a process for formation thereof are disclosed. The EEPROM flash memory cell includes: a source; a drain; a gate insulating layer disposed upon a channel between the source and the drain; a floating gate electrode disposed upon the gate insulating layer and facing toward the channel; and a control gate electrode disposed upon the floating gate electrode across an intermediate insulating layer; and further includes, an erasing electrode for contacting with at least one side of the floating gate electrode at least at one or more spots thereof across a tunneling insulating layer.

Abstract: The invention provides a semiconductor integrated circuit device, which minimizes an increase in the physical and logical size, allows data transfers invoked by a large number of interrupts, and improves the processing efficiency. This semiconductor integrated circuit device is applied to a single chip microcomputer and includes function blocks such as CPU, data transfer controller DTC, ROM, RAMI, RAMP, timer, pulse output circuit, serial communication interface SCI, A/D converter, IOP0-11, interrupt controller, and bus controller BSC. The internal address bus IAB and the internal data bus IDB are connected to CPU, ROM, RAMI and BSC. The internal address bus PAB and the internal data bus PDB are connected to BSC, RAMP, timer, pulse output circuit, SCI, A/D converter, interrupt controller, and IOP0-11. Further, PDB is connected to DTC.

Abstract: A method for forming a wiring layer for a semiconductor device is disclosed. During the formation of a VLSI-scale device having a contact hole with a large aspect ratio, metal layers are filled into the contact hole without spatial discontinuities, and a first wiring metal deposition process is carried out by applying a chemical vapor deposition (CVD) process. Compared with a conventional method, even if a thin film of aluminum is deposited, the wiring metal film can be deposited into the contact hole without spatial discontinuities. The upper opening of the contact hole may remain wide after deposition of the first wiring layer, and the wiring metal atoms may easily move into the contact hole upon reaching the wafer during a second wiring metal deposition. The disclosed invention may provide for superior wiring metal filling characteristics as compared with conventional methods.

Abstract: A method for forming a contact between a conductive layer and a portion of the substrate during manufacture of a semiconductor device is disclosed. The process includes the steps of: (a) covering a semiconductor substrate with an insulating layer, and forming a contact hole on the portion where a contact is to be formed; (b) forming a metal layer on the whole surface of the substrate, and implanting positive ions into the metal layer; and (c) heat-treating the whole substrate so as to form a silicide layer. The metals used are those which can react with silicon to form a silicide, and may be selected from high melting point metals including Co, Ti, Ta, Ni, Mo, and Hf. The ions used are ions including H+ or halogen element ions, and a heat treatment is carried out so that the implanted positive ions may spread on/in the grain boundaries, or that the positive ions may bond with dangling bonds.

Abstract: A pulse width modulation (PWM) circuit is disclosed for multiple channels. The circuit allows output pulses of a PWM signal for each channel to be distributed not simultaneously but with a time difference so that the power consumption is temporally distributed.

Abstract: A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.

Abstract: A package such as for an image sensing device includes the device, which preferably is a solid state image sensing device converting an optical image to an electric signal, metal bumpers formed on the bonding pads of the image sensing device, leads electrically connected to the bumpers, a dielectric wall hermetically sealing the connection areas of the leads and the bumpers, and surrounding the circumference of a light-receiving region of the image sensing device, a glass lid attached onto the dielectric wall and thereby sealing the light-receiving region, and a package body enclosing the structure except the top surface of the glass lid and an exterior portion of the leads.

Abstract: A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode.

Abstract: Methods of fabricating phase shift masks, which facilitate easy adjustment of the light transmissivity of a field region and the thickness of a phase shift mask, to thereby simplify the production process, and increase its reliability and performance. Embodiments may include the steps of providing a transparent substrate, forming a conductive light shielding layer on the transparent substrate, implanting oxygen ions into the conductive light shielding layer to form a semitransparent film, and selectively etching the semitransparent film to form a phase shift film.

Abstract: A thin film transistor and a fabricating method for a thin film transistor is disclosed which may be suitable for memory cells of a static random access memory (SRAM) or other devices. A thin film transistor according to this invention may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.

Abstract: Color measuring systems and methods such as for determining the color or other characteristics of teeth are disclosed. Perimeter receiver fiber optics are spaced apart from a central source fiber optic and receive light reflected from the surface of the object/tooth being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object/tooth being measured. Under processor control, the color measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention. A method of producing dental prostheses based on measured data also is disclosed.

Abstract: An overload protection and control circuit and methods for electrocoat painting systems is disclosed. A resistive shunt is utilized to generate a voltage proportional to the level of current flow to electrodes in the electrocoat painting system. After amplification, the generated voltage is compared with a reference voltage. If the current exceeds a predetermined level, indicative of an overcurrent condition, a comparator causes a control circuit to disable current flow. A timer is provided to delay re-enabling of current flow for a predetermined delay interval. The control circuit may receive inputs from a control PLC or computer. The control PLC or computer may receive inputs from sensors such as a pH sensor or a membrane monitor. The control PLC or computer may selectively control the control circuit to various electrodes so as to more appropriately operate the electrocoat painting system.

Abstract: A semiconductor device isolating method is disclosed which may include the steps of: forming a buffer layer and an insulating layer on a semiconductor substrate, and etching to remove partially the insulating layer so as to form an opening corresponding to the device isolating region; forming hemispherical polysilicon patterns on the whole surface of the substrate; removing the buffer layer exposed between the HSG-Si patterns on the bottom of the opening, and dry-etching the resultant exposed silicon regions to form a plurality of trenches and silicon poles with a certain depth and length; forming an oxide layer on the inside of the trench, and filling the interior of the trench with polysilicon; and oxidizing the polysilicon filled in the trench to form a device isolating region.

Abstract: A non-volatile semiconductor memory device and manufacturing methods therefor, in which the control gate and floating gate are formed in the form of a single level or planar polysilicon layer so as to solve the problem of step coverage. The floating gate is formed in a self-aligning manner. The method may include the steps of: (a) forming a control gate upon an insulated semiconductor substrate; (b) forming an insulating layer upon the control gate; (c) depositing a polysilicon on the entire surface, etching back the polysilicon, and forming side wall floating gates on sides of the control gate; and (d) doping the substrate using the control gate and the side wall floating gates as masks so as to form source and drain regions.

Abstract: Color measuring systems and methods are disclosed. Perimeter receiver fiber optics are spaced apart from a central source fiber optic and receive light reflected from the surface of the object being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object being measured. Under processor control, the color measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention.

Abstract: In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Abstract: The invention discloses a process for formation of a capacitor for a semiconductor device. The upper node electrode is supported by side wall spacers and a central pole, so that the supporting strength may be reinforced and the surface area may be increased. During the formation of a contact hole, a first side wall spacer is formed, and, by utilizing the first side wall spacer, a contact hole is opened with a greater margin. The upper and lower node electrodes are of a tunnel structure. The central pole of the node electrodes is provided with a hole in it, so that a conductive material may be filled into the hole to form a connecting portion. This connecting portion connects the node electrodes of the capacitor to a source/drain region which is formed on a semiconductor substrate. A thin dielectric film is deposited on the surface of the node electrode, and a plate electrode is formed thereupon, thereby completing the formation of the capacitor.

Abstract: A method for insulating semiconductor elements is disclosed. The method includes steps of: forming a 3-layer semiconductor substrate consisting of an upper conductive layer, a high concentration impurity layer, and a lower conductive layer; carrying out a photo etching to remove the upper conductive layer, thereby opening the high concentration impurity layer; dipping the semiconductor substrate into an aqueous HF solution of a certain ratio, and carrying out an anodizing reaction to convert the high concentration impurity layer into a porous silicon layer; and carrying out a wet oxidation to convert the porous silicon layer into a buried oxide layer.