Abstract: A system and method is disclosed for constructing a digital model of an object. The system includes an imaging system for generating object surface scan data from a plurality of surface scans, the surface scan data having a first resolution and representing the object from a plurality of viewpoints. The imaging system further generates image data having a second, higher resolution than the surface scan data for representing the object from the plurality of viewpoints. The system further includes a data processor for iteratively registering the surface scan data for the plurality of surface scans, using the image data, and for reconstructing substantially seamless surface texture data for the model using weights that reflect a level of confidence in the data at a plurality of surface points.

Abstract: A method to reduce the power dissipation of a system by omitting an unnecessary CPU throttling operation in a power management apparatus that performs the CPU throttling operation. A power management apparatus 10 is constituted by an event detecting section 12 to detect an event in a system, an activity detecting section 14 to decide whether the system is in a busy state or in an idle state by checking whether or not there is activity in the system, and a clock control section 16 to execute CPU-clock control. The control section 16 does not perform an unnecessary CPU throttling operation, by stopping the CPU throttling operation when the system is in the idle state and performing the CPU throttling operation only when the system is in the busy state. With this, the power dissipation of the system can be considerably reduced.

Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.

Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.

Abstract: Disclosed is a system and a method for combining the computational resources of numerous embedded devices to enable any of them to perform complex tasks like speech recognition or natural language understanding. A distinguished master device communicates with a network of embedded devices, and organizes them as the nodes of a neural network. To each node (embedded device) in the neural network, the master device sends the activation function for that node and the connectivity pattern for that node. The master device sends the inputs for the network to the distinguished input nodes of the network. During computation, each node computes the activation function of all of its inputs and sends its activation to all the nodes to which it needs to send output to. The outputs of the neural network are sent to the master device. Thus, the network of embedded devices can perform any computation (like speech recognition, natural language understanding, etc.) which can be mapped onto a neural network model.