Abstract: A dispensing pacifier for administering small quantifies of a liquid such as a medicine to an infant. The dispensing pacifier has a nipple member with a cavity for retaining and dispensing the liquid, and friction closure means for the nipple member. A flange encircles one end of the nipple member to prevent its ingestion. The nipple member and the friction closure means are connected by hinge means to prevent loss of the closure means.

Abstract: A system including in combination matched semiconductor elements in a monolithic integrated circuit together with an inexpensive encapsulation. Good electrical matching of individual components in an integrated circuit is achieved by predetermined placement and orientation of the matched components on the semiconductor element. The match is maintained through the assembly steps comprising mounting of the semiconductor element on a metallic support and subsequent encapsulation of the assembly. Best matching for devices located substantially in a {111} plane is achieved by symmetrical placement about a <211> direction.

Abstract: A protective coating composition for photoresist layers comprising an aqueous solution of a vinyl alcohol polymer, at least one surfactant having wetting properties and at least one surfactant having lubricant properties is disclosed. An improved process for forming a photoresist pattern employing this protective coating composition is also disclosed. The composition and process are particularly useful in the fabrication of semiconductor devices.

Abstract: A CMOS circuit having high voltage capability is provided. At least one P channel transistor is coupled between a first voltage node and an output of the circuit. At least two N channel transistors are coupled in series between the output of the circuit and a second voltage node. The at least two N channel transistors each have a separate tub which is connected to the source of each respective N channel transistor. This arrangement of the N channel transistors provides at least one tub which is isolated from the voltage nodes when the output of the circuit is at a potential substantially equal to a voltage present at the first voltage node.

Abstract: An improved metallization system for semiconductor substrates comprising successive layers of at least one barrier metal and tin is disclosed. A semiconductor package comprising a housing of impervious material, a semiconductor device having the metallization system of this invention disposed in the housing and conductor means bonded to the tin on the semiconductor device is also disclosed. The system is of particular usefulness in double stud diode packages.

Abstract: An improved solar energy device has a body of semiconductor material of a first conductivity type with a region of a second conductivity type formed in the body and extending to its surface. A current collection metallization pattern is disposed on the second conductivity type region, with at least three distinct and identifiable current accumulation points connected to the metallization pattern adjacent to the periphery of the second conductivity type region. External electrical connection is made to extract available electrical power from the device at the current accumulation points. The periphery of the device is free of other electrically equivalent external electrical connection areas. These features allow a substantial increase in device efficiency.

Abstract: A surface etchant for silicon comprising an anisotropic etchant containing silicon is disclosed. The etchant provides a textured surface of randomly spaced and sized pyramids on a silicon surface. It is particularly useful in reducing the reflectivity of solar cell surfaces.

Abstract: A germanium mesa transistor is fabricated having an epitaxially grown base region and an aluminum alloy emitter in the epitaxially grown layer spaced from the collector junction, and having a gold-comprising base electrode surrounding the emitter and closely spaced therefrom. The gold contact is formed by photolithographic and selective etching techniques, followed by the formation of the aluminum emitter, which is also formed by photolithographic and selective etching techniques. A key step is the selective removal of the aluminum from the germanium wafer without disturbing the gold contact.

Abstract: This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers.

Abstract: A semiconductor p-n junction structure with improved blocking voltage capability. The improvement results from the addition of a doped layer with limited total doping to the main p-n junction. Such a structure is suitable for diodes, transistors, thyristors and the like.

Abstract: An improved method for forming a guard ring Schottky barrier diode using ion implantation. Diodes formed in accordance with this method require less area but exhibit breakdown voltage comparable to known prior art guarded Schottky barrier diodes. The method is especially applicable to the fabrication of monolithic integrated circuits.

Abstract: Magnetically sensitive semiconductor elements suitable for fabrication in monolithic integrated circuits are disclosed. The elements comprise a semiconductor region of one conductivity type with contact means for providing current flow generally parallel to a major axis, a second orthogonal axis for the application of a magnetic field, and yet a third mutually orthogonal axis along which are disposed at least three second type conductivity regions forming in combination with the first major region a transistor structure with differential properties. In some of the embodiments, low magnetic offset is provided by a selfaligning feature, and power comsumption is minimized by a high resistance region in the device.

Abstract: Non-linear resistors for use as protective devices in electronic circuits. Compositions and methods are disclosed which enable the fabrication of non-linear resistors compatible with other electronic devices in monolithic form. The non-linear resistors disclosed also offer improvements over prior art devices as discrete components.

Abstract: A semiconductor diode package which permits improved thermal and mechanical connection in soldered assemblies. Structural features which result in this improvement comprise double contacting studs having tapered end portions and an area somewhat larger than the semiconductor diode, and an organic encapsulant which seals the diode and the ends of the studs soldered to the diode while leaving the tapered ends of the studs exposed.

Abstract: A solar energy collector comprising a collector plate having a solar energy absorbing surface; a first network of intersecting walls disposed on said collector plate and forming a plurality of cavities thereon; and a second network of three-dimensional members disposed on said first network, said three-dimensional members having reflective surfaces approximately parallel to said collector plate and reflective surfaces in two other dimensions, said three-dimensional members further defining apertures in each of said cavities for admitting incident solar radiation to said cavities. The collector utilizes the absorption advantages of a black body while surpassing the emission characteristics of a selective surface.

Abstract: A metallization system and process for forming bonding pedestals suitable for subsequent gang-bonding of multileaded semiconductor devices. The metallurgical components are selected for corrosion resistance and permit the use of selective etchants for yield enhancement.

Abstract: A high-voltage power transistor is hereinafter described which is able to withstand fluences as high as 3 .times. 10.sup.14 neutrons per square centimeter and still be able to operate satisfactorily. The collector may be made essentially half as thick and twice as heavily doped as normally and its base is made in two regions which together are essentially four times as thick as the normal power transistor base region. The base region has a heavily doped upper region and a lower region intermediate the upper heavily doped region and the collector. The doping in the intermediate region is as close to intrinsic as possible, in any event less than about 3 .times. 10.sup.15 impurities per cubic centimeter. The second base region has small width in comparison to the first base region, the ratio of the first to the second being at least about 5 to 1.

Abstract: A process for improving the continuity of overlayers above an aluminum metallization stripe on a semiconductor device which includes the step of forming a conversion coating on the surface of the aluminium metallization. The conversion coating has a higher etch rate than the aluminum per se, and hence after selective masking, a tapered or sloped edge is produced on the aluminum stripe which is more easily continuously overlayed by the further necessary layers.

Abstract: A metallographic etch is disclosed which removes silicon at a very low rate. The removal of the silicon at a low rate means that the etch is highly controlled. Additional characteristics of the metallographic etch are that it is non-selective and it removes the silicon uniformly. Its special uses are related to an etch which is specially adapted for minimizing the Q.sub.ss charge on a silicon surface, as well as for removing work damage on wafers in which very shallow junction devices are to be formed.

Abstract: A process is described wherein an N-channel silicon gate device operates from a single voltage supply. This process includes an ion implantation step into the gate region of both the load and switch devices for adjusting upwards the threshold voltage of such N-channel silicon gate load and switch devices. This ion implantation of the gate region utilizes the dosage and ion implant energy as factors in determining the change in the threshold voltage. The ion implantation is in a region essentially at the surface of the gate region and as such appears to be a change in the Q.sub.ss term of the device. The effect of the ion implantation is to increase upwards the threshold voltage of the structure as compared with the expected threshold voltage based on the resistivity level of the starting material of the wafer. The overall effect of this process is to provide an active device having a higher output voltage than can be expected from using the starting resistivity material.