Abstract: A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is connected to other transistors and other IC components through interconnects formed on top of such self-aligned contact windows.

Abstract: The present invention comprises a distributed data processing system including a plurality of data processing elements for expeditiously performing an encoding or prediction function pursuant to a context-based model in an adaptive, optimal and time-progressive manner. The distributed data processing system, having access to each symbol of an input data string at each clock cycle, adaptively generates context-relevant data sets which provide the best model for coding or prediction based on the input symbols. Each symbol and its best model for encoding or prediction emerge concurrently from the system, resulting in a favorable time complexity of O(n) for an n-symbol input data string.

Abstract: Nonlinear optical cavities comprising a single or multiple ring paths for use with diode lasers are presented. In one embodiment, the total internal reflection surface of a monolithic or composite cavity is fabricated into a plurality of nonparallel planes. In another embodiment, a composite cavity with either a single end piece or a plurality of end pieces bound to a nonlinear resonator crystal is used to generate either a single or multiple ring paths. In several of the embodiments, incident laser beams entering one end of the cavity follow the ring paths and transmit from the other end of the cavity as a plurality of second-harmonic beams with a pre-defined spatial layout.

Abstract: Improved processes for generating a structure having beveled edges are presented. In a preferred embodiment, two photoresist layers are successively deposited on top of the target material, e.g., a metallization film. The intermediate photoresist layer is developed beyond the lithographically delineated boundaries of the top photoresist layer, forming deep recesses. These recesses remain unchanged during the subsequent etching step, resulting in pre-defined edge profiles in the target material.

Abstract: A method and apparatus are presented for tolerating up to k faults in a d-dimensional mesh architecture based on the approach of adding spare components (nodes) and extra links (edges) to a given target mesh where m spare nodes (m.gtoreq.k) are added and the maximum number of links per node (degree of the mesh) is kept small. The resulting architecture can be reconfigured, without the use of switches, as an operable target mesh in the presence of up to k faults, regardless of their distribution. According to one aspect of the invention, given a d-dimensional mesh architecture having N=n.sub.1 .times.n.sub.2 .times.. . . .times.n.sub.d nodes, the fault-tolerant mesh can be represented by a diagonal or circulant graph having N+m-k nodes, where m.gtoreq.k. This graph has the property that given any set of k or fewer faulty nodes, the remaining graph, after the performance of a pre-determined node renaming process, is guaranteed to contain as a subgraph the graph corresponding to the target mesh M so long as d.