Abstract: An n-bit serial shift register in an ink jet print head operates in a print mode or a test mode. When the shift register is operating in the print mode, n bits of print data are serially scanned into n number of bit registers and are then latched out to heater addressing logic circuitry in the print head to control a print operation. When the circuit is operating in the test mode, x bits of test point data from x number of test nodes in the print head are loaded in parallel into x number of the n number of bit registers, and are then serially scanned out to a test data output. In this manner, a single shift register may be used to scan in print data and scan out test data, thereby providing observability and controllability of the internal logic nodes of the print head while minimizing logic size and the number of input/output connections on the print head.