Abstract: Fluid ejection head assemblies, fluid ejection devices, and methods for improving fluid sealing of fluid ejection head assemblies. One such fluid ejection head assembly includes a substrate cavity and a substantially planar surface surrounding the substrate cavity. The substantially planar surface contains at least one external vent, at least one internal vent channel, and a plurality of vents in fluid flow communication with the substrate cavity and providing fluid flow communication between the internal vent channel and the external vent. The plurality of vents, the at least one external vent and the at least one internal vent channel are disposed in fluid flow communication with an environment external to the substrate cavity for flow of a gas associated with an adhesive at least partially disposed in the substrate cavity, to the environment during the curing of the adhesive.

Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern.

Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.

Abstract: An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: A method for creating a reference for a first position on a substrate edge. A first reference point is selected relative to a circumference of the substrate edge, and a second reference point is selected relative to a bevel of the substrate edge. A first distance along the circumference of the substrate edge between the first reference point and the first position is identified as a first coordinate, and a second distance along the bevel of the substrate edge between the second reference point and the first position is identified as a second coordinate. The first coordinate and the second coordinate are used as the reference for the first position.

Abstract: A data collection system. A data input form receives data, and a message queue receives the data from the data input form, and temporarily manages the data until the data collection system can process the data. A temporary data storage temporarily stores the data received by the message queue while waiting for the data collection system to process the data. A transaction manager receives the data from the message queue and processes the data. A data logger logs the processing transactions of the transaction manager. A data loader receives the data from the transaction manager and prepares the data for storage. A data storage device receives the data from the data loader.

Abstract: A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays, and in a second plot are plotted versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays. A first point is identified on the second plot having a largest numerical difference, and the circuit simulator path delay for the first point is identified. A corresponding point on the first plot having the circuit simulator path delay is found, and the percentage difference for the corresponding point is identified. A combination of both the circuit simulator path delay and the percentage difference is used as the timing margin.

Abstract: A method for improving the operation of an electrophotographic printer. The method includes providing an electrophotographic printer containing a laser scanning unit. A torsion oscillator for the laser scanning unit is enclosed in closed compartment. The closed compartment includes side walls having first and second side wall edges, a bottom wall attached on the first side wall edges, and a cover attached adjacent to the second side wall edges. The closed compartment is sufficient to reduce stray air currents from adjacent the torsion oscillator thereby improving the operation of the electrophotographic printer.

Abstract: An improved ink jet printhead for an ink jet printer and method therefor. The printhead includes a semiconductor substrate containing ink ejection devices. A thick film layer is attached to the substrate. A nozzle plate is attached to the thick film layer. The nozzle plate contains a plurality of ink ejection nozzles corresponding to the ink ejection devices. The printhead contains flow features having a height dimension and a width dimension formed therein for flow of ink to the plurality of ink ejection devices for ejection through the nozzles. At least a portion of the flow feature dimensions for at least one of the nozzles is formed in both the thick film layer and laser ablated in the nozzle plate, wherein the thick film layer contains at least 12% of the flow feature dimensions.

Abstract: A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in the circuit design, calculate an original rise delay, apply a negative bias temperature instability model to determine a parameter shift, determine a new rise number from the parameter shift, and calculate a new rise delay by original rise delay* (original rise number)/(new rise number).

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: A polyimide photoresist for thick film flow features adheres to a polyimide nozzle plate or other materials, without the use of an adhesive material between the two surfaces. Further, the photoresist can utilize an acrylate UV initiator, which can reduce the potential for HF to interact with the ink, and which can cause flocculation and eliminate the need for extremely long postbake cures used to remove HF from the photoresist. In another embodiment, an epoxy adhesive containing a dicyandiamide catalyst can be used to improve adhesion between polyimide films and a respective substrate.

Abstract: A method of micro-machining a semiconductor substrate to form through slots therein and substrates made by the method. The method includes providing a dry etching chamber having a platen for holding a semiconductor substrate. During an etching cycle of a dry etch process for the semiconductor substrate, a source power is decreased, a chamber pressure is decreased from a first pressure to a second pressure, and a platen power is increased from a first power to a second power. Through slots in the substrate provided by the method can have a reentrant profile for fluid flow therethrough.

Abstract: An improved ink jet printhead and method therefor. The printhead includes a single semiconductor substrate with ink ejection devices and a nozzle plate adjacent to the semiconductor substrate, the nozzle plate with first ink ejection nozzles for ejecting first ink drops having a first volume and second ink ejection nozzles for ejecting second ink drops having a second volume different from the first volume, wherein the first volume is defined by first flow features of the printhead having a first thickness and the second volume is defined by second flow features having a second thickness that is different from the first thickness.

Abstract: An optical apparatus compensates for imaging errors associated with the sinusoidal angular scan rate of a light beam reflected from a bidirectional scanning torsion oscillator. The compensation is achieved by a combination of pre-scan optics positioned between the source of the light beam and the scanning torsion oscillator, and post-scan optics positioned between the scanning torsion oscillator and an imaging surface of an imaging device. Based on the optical characteristics of its components, the post-scan optical system causes deflection of the light beam in the scan direction. To compensate for the sinusoidal scan rate, the deflection caused by the post-scan optical system is greater at the opposing edge positions of the imaging surface than at a central position. In this manner, the scan rate of the light beam at the first and second edge positions is substantially equivalent to the scan rate at the central position.

Abstract: A micro-fluid ejection device for ultra-small droplet ejection and method of making a micro-fluid ejection device. The micro-fluid ejection device includes a semiconductor substrate containing a plurality of thermal ejection actuators disposed thereon. Each of the thermal ejection actuators includes a resistive layer and a protective layer for protecting a surface of the resistive layer. The resistive layer and the protective layer together define an actuator stack thickness. The actuator stack thickness ranges from about 500 to about 2000 Angstroms and provides an ejection energy per unit volume of from about 10 to about 20 gigajoules per cubic meter. A nozzle plate is attached to the semiconductor substrate to provide the micro-fluid ejection device.

Abstract: A device surface of a substrate is dry-sprayed with a polymeric material (e.g., a photoresist) to provide a spray-coated layer on the surface of the substrate. The spray-coated layer has a thickness ranging from about 0.5 to about 20 microns. Flow features are formed (e.g., imaged and developed) in the spray-coated layer. A nozzle plate layer is applied to the spray-coated layer. The nozzle plate layer has a thickness ranging from about 5 to about 40 microns and contains nozzle holes formed therein to provide the micro-fluid ejection head structure.

Abstract: A heater chip for a micro-fluid ejection device having enhanced adhesion between a resistor layer and a protective layer. The heater chip includes a substrate, a resistive layer deposited adjacent to the substrate, and a substantially non-conductive protective layer adjacent to the resistive layer. The protective layer is selected from a titanium-doped diamond-like carbon thin film layer, and a single thin film diamond-like carbon layer having at least a first surface comprised of more than about 30 atom % titanium.