Abstract: A method and structure for measuring the minimum lock frequency of a delay locked loop (DLL) within a programmable integrated circuit device such as a field programmable gate array (FPGA). The device is temporarily configured such that one DLL is programmed as a ring oscillator (RO) and connected directly to the input terminal of a second DLL (the DLL under test). Optionally, the RO is connected to the DLL under test through a divider to provide a lower DLL drive frequency. To test the DLL, the RO frequency is decreased until the DLL under test fails to lock. The frequency of the RO at that point is measured by comparing its output signal to the known frequency of an external clock source using two counters, and decremented until the DLL locks successfully. The lock frequency of the DLL under test is then computed from the ratio of the counter values.