Abstract: A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.

Abstract: A data buffer memory management method and system is provided for increasing the effectiveness and efficiency of buffer replacement selection. Hierarchical Victim Selection (HVS) identifies hot buffer pages, warm buffer pages and cold buffer pages through weights, reference counts, reassignment of levels and ageing of levels, and then explicitly avoids victimizing hot pages while favoring cold pages in the hierarchy. Unlike LRU, pages in the system are identified by both a static manner (through weights) and in a dynamic manner (through reference counts, reassignment of levels and ageing of levels). HVS provides higher concurrency by allowing pages to be victimized from different levels simultaneously. Unlike other approaches, Hierarchical Victim Selection provides the infrastructure for page cleaners to ensure that the next candidate victims will be clean pages by segregating dirty pages in hierarchical levels having multiple separate lists so that the dirty pages may be cleaned asynchronously.

Abstract: In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.

Abstract: The invention relates to a tunable on-chip capacity circuit for a semiconductor chip (10) mounted on a substrate (30) and including a plurality of power supply decoupling capacitors (20-23) which can be selectively activated or deactivated by being switched on or off the power supply system. An on-chip detecting circuit (32) determines a circuit specific load/unload frequency of the on-chip power supply network, and on-chip control means (28, 33) responsive to signals of the detecting circuit increases or decreases the total of the on-chip capacity (CSD) by selectively activating or deactivating power supply decoupling capacitors (20-23). Off-chip path impedances (LMC, RMC), an off-chip capacity (CM) and the total on-chip capacity (CC), including the plurality of power supply decoupling capacitors (20-23) and parasitic on-chip capacities (CP), form a resonance loop (40) which is tunable by changing the total capacity (CSD) of the on-chip power supply decoupling capacitors.

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract: The invention relates to a testable on-chip capacitor cell 10 including a decoupling capacitor (Ci) which can be disconnected from the power distribution network and discharged through a cell internal discharge circuit. An externally controllable switch (Si) connects in a first switching position the decoupling capacitor to the power supply system and disconnects in a second switching position the decoupling capacitor from the power supply system and connects it to a resistor (Ri) which is part of the discharge circuit. An off-chip control unit (16) is provided for toggling the switch with a frequency fT between its first and second position to perform a capacitor test operation. By a current measurement device the averaged power supply current demand of the decoupling capacitor is measured when switch (Si) is toggled. The actual capacity of the decoupling capacitor is determined as a function of the power supply voltage, of the switch toggling frequency (fT) and of the averaged power supply current measured.

Abstract: In order to provide a more efficient method and system for data lookups, it is proposed to provide the known CAM (100) with an additional comparator (301). The comparator (301) does not comprise a memory circuit and therefore allows a faster comparison of input data (D0 to D31) with compare data (C0 to C31) than the known compare circuit (106). In addition, it is proposed to temporarily inhibit forwarding of the output signal of the specific CAM circuit into which the input data (D0 to D31) are written, in order to avoid forwarding of a wrong match signal to the data processing system.

Abstract: In order to integrate two FIFOs such as a transmitting FIFO and a receiving FIFO into one FIFO so that a memory area is effectively used, a FIFO memory device 10 comprises a transmitting FIFO control section 20 for writing transmission input data to a memory 100 and outputting the transmitted data written to the memory 100 in order of the data inputting, a receiving FIFO control section 30 for writing receipt input data to the memory 100 and outputting the received data written to the memory 100 in order of the data inputting, a first pointer register 26 for storing the write address of the transmitted data or the read address of the transmission input data in the memory 100, and a second pointer register 36 for storing the write address of the receipt input data or the read address of the receipt output data in the memory 100.

Abstract: A method and system for controlling references to system storage. Milli-code mode provides a flexible technique for overriding storage controls associated with referencing system storage of a data processing system. The storage controls to be overridden are not replaced and therefore, a restore of the previous contents of those controls is not necessary. This allows for an increase in system performance and an increase in the efficiency and flexibility of the system. In addition to the above, a system request instruction is provided, which enables flexibility in the manner in which system requests are executed. The flexibility of the system request instruction reduces the number of instructions needed to perform system requests.