Abstract: A multiprocessor computer system and associated method having processing error detection capability is disclosed for error-free processing of an instruction set. The instruction set is replicated and processed substantially in parallel through a plurality of processing nodes of the computer system. Each processing node collects a compressed hardware signature commensurate with and derived from the execution of the instruction set. Subsequent instruction set processing, the collected hardware signatures from each processing node are compared and the presence or absence of a processing error is determined with reference to a predetermined voting scheme. Processing of the instruction sets through the plurality of processing nodes is typically asynchronous with synchronization occurring subsequent each processor's execution of the instruction set, such that each processor can be driven by an independent clock.

Abstract: An integrated circuit ("IC") chip is provided having both a public key cryptographic engine and a fuse array thereon. The fuse array is hardwired to the public key cryptographic engine and is encoded with a private key for use by the cryptographic engine. Specifically, prior to encapsulation of the IC chip, the fuse array is encoded using a laser ablation process. Upon encapsulation, the private key is permanently sealed and secured within the IC chip. The fuse array may also have a public key hash value and a serial number encoded therein.

Abstract: An integrated circuit ("IC") chip is provided having both a public key cryptographic engine and a fuse array thereon. The fuse array is hardwired to the public key cryptographic engine and is encoded with a private key for use by the cryptographic engine. Specifically, prior to encapsulation of the IC chip, the fuse array is encoded using a laser ablation process. Upon encapsulation, the private key is permanently sealed and secured within the IC chip. The fuse array may also have a public key hash value and a serial number encoded therein.