Abstract: The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both.

Abstract: The present invention utilizes bypass circuitry to shorten the cycle time of a cache memory by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time.

Abstract: A semiconductor chip carrier includes a plurality of distributed high frequency decoupling capacitors as an integral part of the carrier. The distributed capacitors are formed as a part of the first and second layers of metallurgy and separated by a layer of thin film dielectric material built up on a substrate. The distributed capacitors are positioned to extend from a ground pin of one of the layers of metallurgy to a plurality of mounting pads which are intergral parts of the other of the layers of metallurgy. A semiconductor chip is mounted to the mounting pads and receives electrical power and signals therethrough. The distributed capacitors decrease electrical noise associated with simultaneous switching of relatively large numbers of off-chip drivers which are electrically connected to the semiconductor chip.

Abstract: In a switching exchange for circuit-switched/synchronous traffic (CS) and packet-switched/asynchronous data packet traffic (PS), transmission lines communicate with FIFO buffers interconnected by a data bus on which information is transferred in periodic frames. CS traffic is collected in FIFO input buffers in minipackets each carrying a local routing address. The last minipacket per frame period is identified by a special end tag. Once per frame a daisy-chain signal propagates through access control lines to sequentially read out from FIFO input buffers all CS minipackets up to the next one having a special end tag, transferring them through the data bus to FIFO output buffers. Thereafter a token access mechanism starts enabling selective PS data packet transfer between FIFO input and output buffers. When a new frame begins, and PS data packet transfer is interrupted for a CS minipacket readout process, and thereafter transfer of the interrupted PS packet is resumed.

Abstract: A tape support which provides several different functions in a reel-to-reel tape drive is disclosed. The tape support provides means for sensing tension in the tape, buffers or decouples the tape at the magnetic head from any perturbations arising at the take-up reel, and reliably guides the tape along the tape path. The tape travels along an arcuate surface of the tape support on an air bearing. A port in the arcuate surface senses pressure between the tape and the arcuate surface. This pressure is communicated to a transducer which provides an output representing the tension on the tape. Flanges on the ends of the tape support provide guiding of the tape over the air bearing and also provide venting of the air bearing to prevent tape vibration. A purge line expels a gaseous medium out of the sense port thereby keeping the sense port clear of contaminants.

Abstract: A GaAs differential current switch (DCS) logic family is disclosed. Two cross-coupled, push-pull output buffer stages are coupled to the DCS logic circuit to increase the gain and to improve noise margins. The circuit is compatible with other GaAs logic families such as super buffer logic (SBL) or source follower logic (SFFL).

Abstract: Apparatus for handling and positioning thin flexible gummed articles which are stuck in spaced sequence to a webbing which extends along a predetermined path in the machine. A vacuum holding chuck holds the gummed articles by suction and moves horizontally causing simultaneous synchronized movement of the webbing. The webbing goes around the sharp edge of a stripping plate and the vacuum holding chuck continues its straight line motion so that the thin flexible gummed article is stripped from the webbing. The article is then positioned and pressed into contact where it is to be used. The vacuum holding chuck returns to its starting position for the handling of the next article.

Abstract: The multiplexing circuit disclosed herein combines multiple input signals into a common output by allowing ternary signals to pass from multiple input circuits to a common output circuit. The circuit combines ternary signals with minimum feedback between input circuits. The circuit is passive, has minimum attenuation, and a small number of components.

Abstract: A power supply system, which supplies a number of different A.C. and D.C. voltage levels to a plurality of loads, is monitored at a number of points for undervoltage, overvoltage and/or overcurrent fault conditions. A diagnostics logic circuit, which is formed from relatively inexpensive, readily available logic units, generates a BCD code signal indicating a fault in response to the occurrence of a fault condition at one of the monitored points. The system responds to this BCD fault indicating code signal by, on the one hand, protecting the power system by actuating a main relay to open the A.C. power line to the system and generating a shutdown signal applied to a pulse width modulator of a converter in the system and, on the other hand, by driving a seven-segment display which displays a numeral to indicate the location of the fault condition.

Abstract: Monitor circuitry is placed in the closed loop of a phase-locked loop (PLL) circuit and is capable of detecting the existence of an out of frequency window condition and outputting a control signal when the PLL is operating outside the predetermined narrow frequency window. Recovery circuitry, including a phase frequency detector with a wide acquisition range, temporarily replaces the normal phase detector of the PLL, responsive to the control signal from the monitor circuitry. When the monitor circuitry determines that the PLL is back within the predetermined narrow frequency window, the PLL phase detector is switched back into the PLL loop and the phase frequency detector is removed from the PLL loop. The PLL phase detector is then able to lock in on the incoming data stream.

Abstract: A programmable fault injection tool (PFIT) for the texting of the diagnostic capabilities of a computer or digital processing system is disclosed. The PFIT is made up of event compare hardware and error injection hardware.The event compare hardware of the PFIT is user programmable through menu-driven software to compare a particular stored event, either a digital word or sequence of words, with an event measured within the system under test. The stored event can be changed by the user under program control so as to provide a generalized fault injection tool. In addition, the tool includes a mask memory that allows certain bits in a word to be masked, or ignored, when the state of the bit within the word is inconsequential.The error injection hardware of the PFIT is controlled by the event compare hardware to inject faults by short circuiting voltage nodes within the system under test to ground or a supply voltage.

Abstract: An improved thin magnetic layer which is suitable for use in magnetic head pole piece applications and a method of manufacture therefor are disclosed. The magnetic layer is a single phase composition of NiFe and Al.sub.2 O.sub.3. The magnetic layer is manufactured by cosputtering from a single, two phase sputtering target, or from separate NiFe and Al.sub.2 O.sub.3 sputtering targets. The single phase composition results in increased abrasion resistance without degradation of the magnetic properties of the layer.

Abstract: A cartridge receiver with a tray pivotally coupled to a cover pivots from a cartridge receiving position to an operating position in a limited amount of vertical space. A cartridge is guided into and properly aligned within the tray in the receiving position and the cover is then closed and the cartridge receiver latched into an operating position. A plunger attached to the cover exerts a downward force on the cartridge when the cover is closed. Pins attached to the frame align and support the cartridge when the cartridge receiver is in an operating position. A threading pin is coupled to the cover and the tray for engaging a cartridge leader block and a bridge is attached to the tray to align the leader block with the threading pin. The leader block is guided back into the cartridge when the tape is rewound. A cartridge present sensor, a file protect sensor, and a latch sensor are also employed as part of the cartridge receiver.

Abstract: A type band for a printer comprises a track of marks to be scanned (timing marks) at least one of which is obliquely positioned relative to its adjoining marks. The centers of all marks are equidistantly spaced. When the horizontally moving type band is vertically displaced, the time spacing of the scanning signal of the obliquely positioned timing mark is changed over the scanning signal of its adjacent timing mark. The magnitude of the vertical displacement of the type band is derived from the change in this time spacing. The displacement data thus obtained permit compensating for the vertical displacement of the type band (using, for instance, a stepper motor).

Abstract: By hydrolyzing an organoalkoysilane monomer at high concentration in solution to form a silanol, allowing the silanol to age to produce a low molecular weight oligomer, spin-applying the oligomer onto a substrate to form a discrete film of highly associated cyclic oligomer thereon, heat treating the oligomer film to form a modified ladder-type silsesquioxane condensation polymer, and then oxidizing the silsesquioxane in an O.sub.2 RIE, an organoglass is formed which presents novel etch properties. The organoglass can be used as an etch-stop layer in a passivation process.

Abstract: An improved sense circuit for determining the data state of a memory cell in a multilevel storage system is disclosed. The sense circuit includes at least two differential voltage level sensing circuits. A first differential voltage level sensing circuit compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell charge level and a first reference voltage level, thereby providing at least one first binary data output signal. The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal. The adjusted data input signal corresponds to a function of the first data input signal.

Abstract: A masking circuit for a multiprocessor system is disclosed. The masking circuit senses the existence and type of commands stored in the command status registers associated with the system processors. Masking begins if it is determined that information needed by one processor is located in the cache memory of another processor and is to be flushed to the main memory, which is accessible by the first processor. The masking circuit masks the command present in the command status register associated with the first processor, for the first processor to access the main memory, until after the information has been flushed from the cache to the main memory. The first processor is thus prevented from accessing the main memory until after the information has been flushed thereto.

Abstract: Nodule formation in a continuous electroless copper plating system is minimized by independently controlling the dissolved oxygen contents on the plating solution in the bath and in the associated external piping. The level of dissolved oxygen in the plating tank is maintained at a value such that satisfactory plating takes place. At the point where the plating solution leaves the tank, additional oxygen gas is introduced into the solution so that the level of dissolved oxygen in the plating solution in the external piping is high enough to prevent any plating from taking place in the external piping and so that in the external piping the copper is etched or dissolved back into solution. At the end of the external piping, the dissolved oxygen level is reduced so that the dissolved oxygen level of the plating solution in the tank is maintained at the level where plating will take place.