Abstract: The present invention describes an extraction device for removing components, such as leaded integrated circuit packages, from a printed circuit board to which their leads are soldered. The device, under operator control, is designed to captivate the component and to apply to it an extraction force which has a predetermined magnitude independent of the operator's judgment. Accordingly, when all of the component solder joints at the printed circuit board have been sufficiently reflowed, the device automatically withdraws the component from the board into itself. Damage to the board or the component as a result of the extraction process is virtually eliminated through the use of the device.

Abstract: Disclosed is a selector switch for use in forming an asynchronous network of concurrent processors where the selector switch receives a message from one input port and transmits it to one of two output ports. A path through the network which has been established can be cleared should it become apparent that that particular path has become locked in due to a malfunction of a component in one of the nodes or switches in the network.

Abstract: The present disclosure describes a universal leadless chip carrier mounting pad layout for an interconnection medium such as a printed circuit board, which accommodates a wide range of chip carrier sizes. Thus, there is eliminated the traditional method of providing custom pad layouts homologously configured as to numbers of pads and their arrangement, in specific chip carriers. The universality of the present pad layout makes it especially desirable for prototype designs, and integrated circuit chip "burn in" and test procedures.

Abstract: A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction.

Abstract: This disclosure relates to a system and method for realizing asynchronous sequential circuits in a manner analagous to the stored state method for synchronous sequential circuits. The circuit is a stored state circuit including a memory and an output register with an input line and an input request line coupled to the memory and the output register having an output data line and an output acknowledge line. A pulse generator is coupled to the input request line so as to generate a timing signal, for transmission to the output register, a fixed period of time after receipt of a request signal on the input request line. A request signal will not appear on the input request line until a data signal on the input data line has stabilized. Furthermore, an acknowledge signal will not be generated until a signal on the output data line has stabilized.

Abstract: An electronic recognition circuit is described for use in bar code reader systems having postal and commercial applications. Such systems may be required to read codes which are of relatively poor print quality. The present circuit utilizes statistical auto-correlation techniques to reject extraneous ink dots and minor print voids commonly associated with such printing. Additionally, the circuit is skew tolerant and both position and velocity independent of the bar code being processed.

Abstract: In an approximate content addressable storage system data words are stored in a two dimensional storage array with each data character therein stored in a particularly associated storage row and each data word individually and sequentially character-by-character stored column-by-column. In searching the array for a particular word each storage row associated with a character in the search word is accessed in a manner biased to that character's position in the search word so that the search for all characters occurs effectively in parallel. A searched for character located in its proper position is given maximum value with decreasing value accorded to searched for characters detected one or more positions removed from the proper position in the search word. The value derived for each character is totalled with similar values derived from all other characters in the search word thus arriving at a value indicative of the approximateness of a stored word with the search word.

Abstract: The present disclosure describes a connector or socket having particular application for LSI/VLSI integrated circuit (IC) packages with cylindrical interface pins. The connector is characterized by the ease with which the IC package may be inserted therein or withdrawn therefrom, despite the large number of pins involved. In achieving this result, the connector utilizes a unique contact design wherein two opposing cantilever type spring members include respective contoured fingers for capturing and firmly holding an IC package pin during normal circuit operation. The connector also incorporates one or more contact release plates, each having a plurality of cam-like apertures operatively positioned with respect to the connector contacts. Actuation of a release plate moves each pair of contact spring members toward each other, thereby opening the area enclosed by the fingers and providing substantially zero force package insertion or withdrawal conditions.

Abstract: In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Abstract: The present disclosure describes a low insertion force connector for use with integrated circuit (IC) packages of the LSI/VLSI type. The connector is characterized by simplicity of design and economy of manufacture. The well known friction-type contact comprised of members which enclose and bear against the pin surface is replaced by a pin-receiving cup loosely fitted in a cavity in the connector body and supported by one extremity of a light spring member. The opposite extremity of the latter may include an integral tail section or a separate solder or wire wrap tail may be affixed thereto. The force required to seat the IC package in the connector is a function of the spring compressive forces and may be made quite low. Removal force for the package is virtually zero. Additionally, a ramp section in the connector is adapted to receive a wedge-like member which bears against the outer surface of the IC package and causes the gradual collapse of the contact springs as the package is seated.

Abstract: This disclosure relates to a wafer scale power interconnect system by which defective circuits on the wafer can be automatically disconnected from the power and ground lines supplied to each of the circuits. The disconnect device employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be destroyed by an excessive current thereby opening the gate. The disconnect device may also be just such a fuse or a current limiter.

Abstract: In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.