Abstract: A two-level signalling or pulse correcting circuit which includes two delay circuits each feeding a section of a bistate output device. Each delay circuit has an individual time modifier circuit responsive to an input pulse duration of greater than a predetermined minimum for increasing the duration of an output pulse from said device to an interval between said minimum duration and a predetermined maximum duration.

Abstract: In a large time-space-time division switching network, particularly one employing a multistage space-division switch, one time-division elementary time is too brief to enable transmission of addresses of crosspoints to be completed through all the stages of the multistage switch, and also provide for transmission of the speech sample. To cope with this situation, two successive network elementary times are used, each elementary time being divied into two half-times, i.e., a first half-time and a second half-time. First half-times are used for transmitting addresses of crosspoints to be closed immediately. Second half-times are used for storing data concerning further crosspoint addresses plus a speech sample. Addresses are propagated through a speech sample path according to a "staggered operation", thereby reducing the requirements for memory dedicated to crosspoint addresses.

Abstract: A system is disclosed for checking and correcting the synchronism of bits stored in a circulating memory which is part of a PCM switching system. Periodically, bits previously written in an addressable memory are read-out and compared to corresponding bits supplied by the circulating memory. In accordance with results of the comparison, a synchronism signal or a fast or slow correction signal is supplied.