Abstract: A DC-DC converter suitable for multiple converter circuit topologies is disclosed. The DC-DC converter utilizes magnetic feedback of the output load current to provide broad inductance control of a magnetic element, while inhibiting saturation of the switched winding or windings of the magnetic element.
Abstract: An apparatus and method for sorption and desorption of molecular gas contained by storage sites of graphite nano-filaments randomly disposed in three-dimensional reticulated aerogel.
Type:
Grant
Filed:
May 7, 2004
Date of Patent:
May 27, 2008
Assignees:
EnerNext, LLC
Inventors:
Ralph C. Struthers, David B. Chang, Reza Toossi, Sion Ahdout, Lijuan Li, Robert G. Palomba
Abstract: The present invention provides a method to improve adhesion of barrier, metal, dielectric interfaces. In the process flow, a first barrier material is formed on a dielectric layer and bombarded with a plasma to effectively push the barrier material into the dielectric interface while leaving a portion of the barrier material over the dielectric. A second barrier material, which may or may not be the same as the first barrier material, is then formed on the remaining first barrier material. Advantageously, the method of the present invention allows the barrier material to be pushed into the dielectric to insure excellent adhesion, which prevents chemical mechanical polishing delamination. Furthermore, the presence of the first barrier material on the sidewalls of via apertures through the dielectric can prevent Cu poisoning from sputtered Cu or CxOy.
Type:
Grant
Filed:
October 8, 2002
Date of Patent:
September 28, 2004
Assignee:
Novellus Systems, Inc.
Inventors:
Karen Chu, Anil Vijayendran, Michal Danek
Abstract: Systems and methods provide common mode termination for input/output circuits. For example, common mode termination may be provided to a bank of input/output circuits by programmably coupling a bus to each pair of input/output circuits. The bus provides a path to ground for common mode signals through a capacitor or, alternatively, the bus may be designed to provide or assist in providing the necessary capacitance.
Abstract: A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block.
Type:
Grant
Filed:
December 19, 2000
Date of Patent:
August 20, 2002
Assignee:
AMI Semiconductor, Inc.
Inventors:
James A. Antone, Melvin W. Stene, Brian R. Kauffmann