Abstract: A battery charger system (100) is provided which includes a charger (110) for supplying charge current and voltage and a battery (120) having a memory (122) for storing charge parameters. The charge parameters comprise battery related information instructing for battery charging. The battery related information stored in the memory (122) may include charge instructions instructing the charger of procedure for charging the battery (122).
Type:
Grant
Filed:
June 28, 1995
Date of Patent:
July 9, 1996
Assignee:
Motorola, Inc.
Inventors:
Robert D. Kreisinger, Arthur G. Burns, Jose M. Fernandez
Abstract: In a CDMA communication system (100) capable of communicating between a receiver (10) and a transmitter (20)direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver chip timing and transmitter chip timing. Transmitter (10) transmits a training bit sequence (31) coded with a spreading chip sequence. The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). The representation of the despreading chip sequence is represented by tap coefficient potentials of the equalizer (400). Receiver chip timing offset is determined based on the tap coefficient potentials.
Type:
Grant
Filed:
June 7, 1993
Date of Patent:
October 25, 1994
Assignee:
Motorola, Inc.
Inventors:
Edward K. B. Lee, Jimmy Cadd, Tracy L. Fulghum
Abstract: A communication method in an adaptive CDMA communication system (100) capable of communicating a direct sequence spread spectrum communication signals which comprise bit sequences coded with spreading chip sequences. The method includes the steps of transmitting a DS-SS communication signal (30) having a training bit sequence (31) coded with spreading chip sequence. The method includes the step of despreading the DS-SS communication signal based on the training bit sequence (31) during a training interval. The DS-SS communication signals is despread by adaptively determining a despreading chip sequence. Then, following the training interval determining chip timing offset during a chip timing interval. Finally, bit timing offset is determined during a bit timing interval following the chip timing interval.
Type:
Grant
Filed:
June 7, 1993
Date of Patent:
October 4, 1994
Assignee:
Motorola, Inc.
Inventors:
Edward K. B. Lee, Jimmy Cadd, Tracy L. Fulghum, Robert S. Babayi
Abstract: A high efficiency amplitude/phase modulation amplifier circuit (100) includes a first (102) and a second (106) high efficiency amplifier. These amplifiers (102 and 106) amplify two constant amplitude/phase modulated signals. A combiner (104) combines the output signals from the amplifiers (102) and (106) to produce a combined signal to a load (108). Two shunt elements (202 and 204) are included to prevent the reactive components of the combined signal from reaching the amplifiers (102) and (106). With no reactive components reflected back, the amplifiers (102 and 106) can remain non-linear even though they are used to amplify an amplitude/phase modulated signal which includes Amplitude Modulation (AM) components.
Abstract: A communication device (100) having a receiver (106) and an audio output device (116) is provided. The communication device (100) includes a digital signal processor DSP (110) for measuring the level of signal energy in a first segment of the frequency spectrum of the received signal to dynamically establish a squelch threshold. The DSP (110) is also used to measure the level of signal energy in a second segment of the frequency spectrum of the received signal. The communication device (100) also includes audio gates (114). The audio gates (114) provides for the unmuting of the audio output device (116) when the signal energy contained in the second segment of the frequency spectrum of the received signal is below the squelch threshold.
Type:
Grant
Filed:
April 3, 1992
Date of Patent:
April 12, 1994
Assignee:
Motorola, Inc.
Inventors:
Mansour Ghomeshi, Chin P. Wong, John W. Simmons