Abstract: Timing facilities are used to provide sequence values that are unique across operating system images. A sequence value includes various components, including timing information and selected information. The selected information is used to provide a sequence value that is unique across a plurality of operating system images. Additionally, the sequence value can include, for instance, a processor identifier component and a placeholder component. The placeholder component ensures that the sequence value is an increasing value, even when the physical clock used to provide the timing information wraps back to zero.

Abstract: Instruction and data registers of processors of a multiprocessing computing system are joined and forked to allow processing in multiple modes of operation. When joined, the registers of the processors each contain a same piece of information, hence generating single instruction and data streams. In contrast, when forked, the registers of the processors contain different pieces of information, thereby generating multiple instruction and data streams. Additionally, information may be stored into partitions of memory and fetched and broadcast by processors local to the particular memory sections thereby resulting in a faster cycle time.

Abstract: A system and method for providing education that includes a database of educational material and a user interface. When prompted by a user through the user interface, the system provides a specific educational session from the database that is directed to satisfying a present business need/solution (e.g., a need for a specific legally binding written document with a customer or supplier). With the invention, the educational session produces a completed version of the legally binding written document. The user interface preferably includes a decision tree providing options for the user to select from different computerized educational sessions relating only to the present business need/solution. While the database includes educational material relating to many business needs/solutions, the decision tree limits user access to only those educational sessions relating to the present business need/solution.

Abstract: Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first register of a first processing engine and at least one second register of a second processing engine. Data is transferred between the first processing engine and the second processing engine through the register pipe without passing through memory. In one embodiment, general purpose registers within the first processing engine and within the second processing engine are employed to implement the register pipe. A control mechanism is provided within each processing engine to dynamically enable or disable the register pipe coupling any two processing engines of the multiprocessor computer system. A technique for broadcasting to multiple register pipes and for implementing barrier synchronization using a register pipe addressed to a processing engine itself are also provided.

Abstract: Synchronization “states” of programmable length imposed on processing nodes are disclosed, the last of which contains an event requiring action by fully synchronized nodes. The nodes are shifted between the states using a shared timing source to ensure synchronization for the event. The first state is a “non-impending event” state where the nodes continue their routine processing; the second state is an “impending event state” closer to the event, and within which nodes “wait” for the event by suspending their routine processing. In the third state, immediately preceding the final, event state, any non-waiting nodes are interrupted for the impending event. The present invention therefore allows some node autonomy during the first state within which the nodes poll at their leisure, and during the second, “wait” state, but during the third, interrupt state, any nodes not yet arriving by polling are interrupted.

Abstract: A physical clock is expanded to enhance its precision. Existing instructions are capable of using the enhanced physical clock. Execution of an instruction begins, which places a value of the expanded physical clock in a physical clock field of a clock representation. The physical clock field is, however, unable to accommodate the value provided by the expanded physical clock. Thus, that value encroaches upon another predefined field of the clock representation. Completion of the instruction is therefore delayed such that the value provided by the expanded physical clock can be accommodated in the clock representation and a correct value for the another predefined field can be provided.

Abstract: A management facility for managing concurrently executable computer processes. The management facility includes a registration mechanism, which enables a plurality of interdependent processes to be considered a part of a topology of logically dependent execution groups, and a termination synchronization mechanism that synchronizes the completion of termination for the processes within the topology. Termination synchronization prevents a process within the topology from completely terminating, even if it has entered normal termination, until all of the processes within the topology have normally terminated. If one of the processes within the topology has abnormally terminated, then notification of this abnormal termination can be propagated to all of the processes within the topology of logically dependent execution groups, since none of them have completely terminated.