Abstract: The present invention comprises a cascode circuit of the type having a first and second FET in a first leg and a third and fourth FET in a second leg comprising. The first and third FETs are switched between an on state and an off state substantially in tandem in response to a level change in an input signal to the cascode circuit. The second and fourth FETs are switched between an on state and an off state substantially in tandem in response to a level change in the input signal and substantially complimentary to the switching of said first and third FETS. A biasing signal is applied to a control electrode of the first FET responsive to transition of the input signal from a first level to a second level. A biasing signal is also applied to a control electrode of the third FET responsive to transition of the input signal from the second level to the first level.

Abstract: A bit line reference circuit for a nonvolatile semiconductor memory device performs a referenced data access operation using a single bit line having upper and lower portions. The circuit has an open bit line structure and includes an upper memory cell string connected to the upper portion of the bit line, and a lower memory cell string connected to the lower portion of the bit line. An upper reference cell string is connected to the upper bit line for providing a reference potential to the upper bit line in response to a first control signal, while the lower memory cell string is selected. A lower reference cell string is connected to the lower bit line for providing a reference potential to the lower bit line in response to a second control signal, while the upper memory cell string is selected. A page buffer is connected between the upper and lower portions of the bit line and accesses data by comparing the potentials on the upper and lower portions of the bit line.