Abstract: According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well.