Abstract: Unused space in a storage medium such as a read only memory is used to store additional fonts, thereby increasing the total number of fonts stored in an apparatus. A portion of the fonts stored in the apparatus are made available to a user using traditional methods. If a key is present or has been added to the apparatus, the additional fonts are made available to the user. Examples of a key include software code, a hardware jumper or a card with a hardware identification or jumper.

Abstract: An apparatus for controlling audio signals having pulse code modulation (PCM) data and methods of operating the same result in efficient modulation of the audio signals. The apparatus for controlling audio signals comprises a PCM data input register configured to store the PCM data. A shift register is coupled to the PCM data input register configured to serially shift the PCM data. A PCM data output register is coupled to the shift register configured to store modified PCM data. An audio magnitude controller is coupled to the shift register configured to control serial shifting of the shift register to provide the modified PCM data.

Abstract: An improved socket connector has flexible interior barriers to prevent incorrect insertion of smaller sized plugs, where a flexible internal barrier is formed on a side of the socket entry leading into the socket cavity, and is composed of a flexible ramp attached from the socket entry, the ramp extending into the socket cavity and having a inner movable end with a vertical barrier, sized and disposed within the socket cavity so that the insertion of a correctly sized wide plug will engage the flexible ramp, riding along and moving the flexible ramp so that the vertical barrier is moved out of a stopping position, allowing the correctly sized wide plug to be fully and properly seated in the cavity, but further sized and disposed within the socket cavity so that the insertion of an incorrectly sized narrow plug will fail to engage the ramp, will not flex the ramp, and will leave the vertical barrier in the stopping position, where it prevents the incorrectly sized narrow plug from being fully inserted into the

Abstract: A method and apparatus for operating a computer system at the interrupt level. Rather than having a primary task list that is interrupted to service interrupts, all tasks derive from interrupts. To this end, interrupt-time data structures and representations are precomputed and represented. The taxonomy of real time data types is organized. It is preferable to include isochronous media, together with supporting algorithms and heuristics.

Abstract: A special bridge device provides a level of isolation between two independent but compatible bus environments such that only addresses and transactions directed to the other environment are passed through, together with associated data and control information. The device includes address and transaction remapping between the two environments.During an initialization phase, this device presents itself to the host system as a simple bus device. In one preferred embodiment, the special bridge presents itself as a mass storage or memory device. The host computer performs the minimal setup for such a device. During initialization of the second bus environment, the special bridge device again presents itself only as a simple device, and preferably is not presented as a bus device to the second system at all.

Abstract: An integrated mounting solution provides a plurality of mounting connections in close proximity to the appliance, and one or more appliances with a compatible, mating mounting connection. In a preferred form, the mounting connections are integrated with the appliance and may take the form of a series of hole, or perhaps projections. In a particularly preferred form, the mounting connections are a series of holes arranged vertically and positioned in a recess designed into the appliance so that the mounting connections are not a prominent aspect of the visual impact of the appliance, yet are readily available for securing an accessory.

Abstract: A method for the loading and unloading of a FIFO in an isochronous transmission mechanism uses descriptor blocks which have both branch addresses and skip addresses. The method can recover from cycle loss by selectively resending or skipping a packet that should have been sent in the lost cycle. The method also works two cycles ahead of schedule, in an attempt to keep the FIFO loaded with all of the packets for two cycles of transmission. The FIFO is filled according to a DMA algorithm and drained according to a Link algorithm where the two algorithms are coordinated to communicate information about lost cycles and current demands or opportunities for transmission. If the Link algorithm detects a lost cycle, it communicates that to the DMA algorithm and the DMA algorithm seeks to compensate appropriately. These two algorithms describe mechanisms for the DMA and Link sides of an isochronous transmitter.

Abstract: An ASIC (Application Specific Integrated Circuit) cell implementation of an ADB (Apple Desktop Bus) bus controller with programmable timing value registers for the Apple Desktop Bus (ADB) has a system interface for connecting to a computer system including an address bus interface, a data bus interface, and a control bus interface, and has an ADB interface for connecting to an ADB peripheral bus. A control state machine within the ADB bus controller uses timing data from the programmable timing value registers to implement the Apple Desktop Bus data signaling and communications protocol on the ADB interface.

Abstract: A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional units, a plurality of register files, and a data router. In the hyperscalar computer architecture, the central memory transfers a plurality of instructions to the instruction buffer. The control unit receives multiple instructions from the instruction buffer, and automatically determines and issues the largest subset of instructions from those received that can be simultaneously issued to the plurality of functional units. Each functional unit receives data from and returns computational results to a corresponding register file. The data router serves to transfer data between each register file and any other register file, the central memory, the control unit, or the I/O control unit.

Abstract: A heat sink and spring clip assembly for removing heat from an electronic module and for holding the heat sink and electronic module to a circuit board, with the heat sink having a finned top surface, and a flat bottom surface larger than the electronic module for holding the electronic module between the bottom surface and the circuit board, with the bottom surface also having a downward extending leg at each corner, each leg ending with a foot for resting on the circuit board and holding the heat sink a fixed distance above the circuit board, and the spring clip for holding the heat sink to the circuit board having a substantially rectangular frame with two opposing torsion bar sides and two opposing leaf spring sides, the sides connected at four corners, and each corner having a downward extending leg with a latching notch for latching into a latching hole in the circuit board when the spring clip is pressed down over the heat sink and the leaf spring sides are compressed.

Abstract: An apparatus and method to accomodate a card designed to operate, with an alternate bus standard within a computer designed to operate with a primary bus standard, where the primary bus standard and the alternate bus standard are not directly compatible. The card is designed to fit within the computer in the available physical space and to connect to a card connector as required for the primary bus. However, the card is designed to be electrically compatible with the alternate bus standard. In a preferred embodiment the card draws power and any other signals, perhaps including clock, that are useful to both bus standards, but the address, data and control bus signals for the alternate bus are delivered to the card through an independent channel. This independent channel can be a separate connector to carry any signals needed for the alternate bus standard, which according to the application may or may not repeat signals already available through the primary bus.

Abstract: A method for bit cell determination and timeout detection for an Apple Desktop Bus, using a counter clocked by a clock generator, according to the steps of: At the start of a bit cell, loading an initial value into the counter and enabling the counter to count down as clocked by the clock generator. Counting down until a low to high transition in the input ADB signal is detected or a terminal count is reached, such that if the low to high transition transition is detected, then enabling the counter to count up, else if the terminal count is reached, then indicating a timeout condition. If the counter is enabled to count up, then counting up until a high to low transition in the input ADB signal is detected or the terminal count is reached, such that if the high to low transition is detected, then stopping the counter and reading a final value to determine the bit cell value, else if the terminal count is reached, then indicating a timeout condition.

Abstract: A DMA controller capable of conditional action under the control of a status register, prespecified parameters, and a condition field of the channel command, and a DMA controller which returns status information to command entry locations that are reserved for this purpose are disclosed. The prespecified parameters may be held in a register having a mask field and a value field, and a test for conditional action may be a masked comparison of the status register and the value field. The condition field determines how the test result is interpreted and allows suppressing or forcing the conditional action during a command.

Abstract: A speech recognition system operating on a computer system, where the speech recognition system uses a language model with embedded structure and attached data values, and the speech recognition system returns recognition results as a reconstructed language model with embedded structure and attached data values. An application program can receive and traverse the embedded structure of the recognition results and use the attached data values to improve the speed and accuracy of interpretation of the speech recognition results.