Abstract: The saturation compensating analog to digital converter has converter circuitry receiving an analog signal and outputting converted data. The converted data from the converter circuitry is processed and filtered to provide a digital data output. The digital data output is received into shift register circuitry before being transmitted for later-stage processing. When the converter circuitry is operating close to a saturated condition, a saturation detector generates a saturation signal. The saturation signal is received at a variable gain circuit which adjusts the gain of the input signal to the converter circuitry. The shift register circuitry also receives the saturation signal and provides an upshift of the digital data to compensate for the associated reduction in input gain provided by the variable gain circuit. In operation, the variable gain circuit is initially set to its maximum output, thus providing the maximum possible input signal to the converter.

Abstract: A multiple mode digital X-ray imaging system providing for preprocessing “binning” of analog pixel signals from a detector array by selectively summing, within the detector array, adjacent pixel charges on a row-by-row basis and selectively summing, within detector array readout circuits, the previously summed pixel charges (by rows) on a column-by-column basis. An array, or mapping, of “defective pixel” flags is used to identify defective pixels within the detector array, with such flags being added to, or inserted into, the incoming data stream for dynamic processing along with the incoming pixel data. A buffer and filter is used to perform still image capture during the radiographic mode of operation and to recursively filter incoming data frames during the fluoroscopic mode of operation by summing a scaled amount of pixel data from prior data frames with a scaled amount of incoming pixel data from the present data frame.

Abstract: Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (“pump up”) or sink (“pump down”) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

Abstract: A signal line driving circuit with power control for selectively reducing internal power dissipation when driving an external load. While driving the external load with a constant current the output voltage generated across such load is monitored. If the load impedance decreases sufficiently to cause the output voltage to fall below a predetermined threshold value and, therefore, cause the voltage across the signal line driving circuit to increase, the magnitude of the power supply voltage is automatically reduced, thereby reducing the voltage across the signal line driving circuit. Such a signal line driving circuit is particularly advantageous as a subscriber line interface circuit (SLIC). As the subscriber goes from an on-hook condition to an off-hook condition and if the subscriber loop is sufficiently short (or low in impedance), a lower power supply voltage is used to minimize the power dissipation of the SLIC while still maintaining the required subscriber loop current.

Abstract: A voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror circuit. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. One voltage divider output voltage is fixed and the other is variable. The input terminal of the differential amplifier circuit branch biased at the fixed potential receives an AC-coupled input signal voltage. The sum of the input signal voltage and the fixed bias voltage is compared against the variable bias voltage. A current mirror circuit, which is activated during conduction by the differential amplifier circuit branch biased at the variable potential, shunts a portion of the current used by the voltage divider circuit that generates the variable potential. This causes the variable voltage divider output voltage to change, thereby introducing hysteresis into the voltage comparison performed by the differential amplifier.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: A switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a chopper stabilized amplified filter circuit which amplifies and low pass filters its input data signal to produce an output signal with an out of band signal frequency component which is at the chop signal frequency and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. An output switched capacitor filter circuit which is synchronized with the chopper stabilized amplified filter circuit filters this signal with a stopband filter frequency response that virtually eliminates such out of band signal frequency component. When used in a closed feedback loop, this filtered signal is used to generate an offset compensation signal that corresponds to the residual offset within the output signal resulting from the amplifying and filtering of the input data signal.

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) enters the low power operational mode in which power consumption is reduced at least for the pipeline subcircuit, but without stopping the supply of clock signals to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode.

Abstract: An extended power ramp table for a power amplifier control loop in a time division multiple access (TDMA) communication system includes a power profile data table and a control data table. The power profile data are used to control transitions of the power amplifier circuit between its on and off states to minimize the number and power levels of spurious and other undesired signals generated by such on and off circuit state transitions. The control data are used to programmably control various performance characteristics of the control loop for the power amplifier circuit, such as controlling the gain of the driver amplifier for the power amplifier control (or reference) signal, controlling the gain and offset of the feedback amplifier for the control loop, and selectively providing a bias current for an external power detection diode. By making the control data user programmable, maximum flexibility in controlling the power amplifier control loop can be achieved.

Abstract: A switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes a chopper stabilized amplified filter circuit which amplifies and low pass filters its input data signal to produce an output signal with an out of band signal frequency component which is at the chop signal frequency and represents an offset and 1/f noise of the chopper stabilized amplified filter circuit. An output switched capacitor filter circuit which is synchronized with the chopper stabilized amplified filter circuit filters this signal with a stopband filter frequency response that virtually eliminates such out of band signal frequency component. The resulting output signal is then converted to a digital signal by an analog-to-digital conversion (ADC) circuit.

Abstract: An input signal voltage clamping circuit that provides asymmetrical, or unipolar, voltage clamping for an input signal terminal of a circuit. For a circuit having a positive power supply voltage relative to its ground, or reference, terminal and an input signal having positive and negative signal peaks, the input signal terminal voltage is clamped at positive and zero voltage levels. The input signal terminal voltage is clamped at a positive clamp voltage level which is intermediate to the power supply and ground potentials when the input signal voltage is greater than such positive clamp voltage. The input signal terminal voltage is clamped at a zero volt level when the input signal voltage is negative.

Abstract: An analog amplifier with a monotonic transfer function converts an incoming analog control voltage into multiple continuously variable discrete analog control voltages which are then used to control the respective gate biases of multiple MOS transistors. The MOS transistors are each connected in series with respective associated resistors and in a laddered parallel configuration with other serial transistor-resistor pairs. This creates a variable impedance circuit which, in accordance with the continuously variable discrete analog control voltages, exhibits a corresponding continuously variable circuit impedance in the form of a continuously variable resistance. This variable resistance forms part of the feedback circuit for controlling the gain of a noninverting operational amplifier circuit. This causes the ratio of the analog output and input signals of such operational amplifier circuit to define a monotonic transfer function.

Abstract: A charge sensitive amplifier with high common mode signal rejection includes an NPN bipolar junction transistor (BJT) and a P-channel metal oxide semiconductor field effect transistor (MOSFET) connected in a totem pole circuit configuration. The BJT base terminal receives a dc reference voltage, the MOSFET gate terminal receives the incoming data signal, the MOSFET drain terminal is grounded and the BJT collector terminal provides the output voltage signal and is biased by the power supply through a resistive circuit element. The MOSFET operates as a source follower amplifier with the transconductance of the BJT serving as the load at the source terminal, while the BJT operates as a common emitter amplifier with the transconductance of the MOSFET providing emitter degeneration. The signal gains of such source follower and common emitter amplifiers are substantially equal and of opposite polarities. Therefore, any common mode signal components due to common mode input signals present at the input terminals (i.