Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: A method of manufacturing integrated circuits based on providing a test column of memory cells in the devices. Cells in the test column are selected by a portion of the addresses which identifies a row in the main array on the device. A test is executed to determine a characteristic of the device, and the results of that test are mapped to the portion of the address which identifies a row in the array. This produces a characteristic code address for the device which indicates the results of the test. Access to the test column on the device is enabled, and a bit is written in response to the characteristic code address in a memory cell on the test column. During manufacture the test column is read in order to classify the device according to the characteristic.