Abstract: A system that couples distributed power generators together as a collective unit for the purposes of selling or purchasing energy from the electrical power grid. The apparatus includes a charge/discharge controller and an adaptive controller. The charge/discharge controller transfers energy generated by the plurality of distributed power generators to the power grid. The adaptive controller directs when the charge/discharge controller transfers energy generated by at least one of the plurality of distributed power generators to the electrical grid.

Abstract: A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b0, and a zero at location a0. The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

Abstract: An integrated circuit includes a self-calibrating resistor circuit comprising a resistor string, a comparator, a state machine, a reference voltage source, and a reference current source. The current source typically comprises a voltage reference, typically a bandgap reference, and a temperature-independent resistor having a value REXT. In operation, a reference current IREF flows through the resistor string. During a calibration period, the voltage across the string is compared to the bandgap reference voltage, VBG, by the comparator, which controls the state of the state machine. The outputs of the state machine turn on or off the resistors in the string until the voltage across the string, VR, is approximately equal to the reference voltage. The resistance of the resistor string is then equal to RBG=VBG/IREF, which is proportional to REXT, and thus is typically independent of process and temperature.

Abstract: A system and method that compensates for a pull-up resistor coupled to a buffer, when the pull-up resistor has an unknown resistance value. The system includes a buffer and a parameter detector. The buffer receives an input signal at a buffer input, and the buffer generates a buffered signal at a buffer output. The parameter detector measures a parameter at the buffer output when the buffer is in a high impedance output state, and the parameter detector generates a buffer control signal based upon the measured parameter. The buffer responds to the buffer control signal generated by the parameter detector.

Abstract: An integrated circuit includes a controlled impedance that remains relatively constant with respect to variations in processing and temperature. The controlled impedance comprises a fixed resistor in parallel with one or more switchable resistors having a resistance value greater than that of the fixed resistance. Control circuitry includes a reference current generator. The reference current is flowed through a tracking resistor formed of the same material (e.g., doped polysilicon) in the same fabrication process as the fixed resistor. Comparators are used to monitor the voltage across the tracking resistor, and control the switching of the switchable resistors in order to obtain a desired effective resistance. Use of the inventive technique to provide a transmission line termination impedance is described in an illustrative embodiment.

Abstract: An integrated circuit package including a die housing an integrated circuit and having a plurality of electrical contact pads on a surface of the die. The electrical contact pads include energizing contact pads for connecting power and ground lines to the integrated circuit, and include data contact pads. The energizing contact pads lie along the path of intersecting first and second directional lines. The intersecting directional lines define four quadrants on the surface of the die, each quadrant containing at least one data contact pad.

Abstract: A clock generator having a ring structure and a chain structure. The ring structure is formed of an even number of serially connected distributed oscillator elements, and the chain structure is formed of an even number of serially connected distributed oscillator elements. The chain structure is coupled across an odd number of oscillator elements in the ring structure. The ring structure and chain structure, when connected together, generate a clock signal that can be extracted from any of the distributed of oscillator elements.

Abstract: When flash memory devices are scaled down into the deep-submicron regime, tub erase is being increasingly deployed because it features lower erase current and better reliability performance than the conventional source-side erase scheme. However, tub erase requires higher voltages to be applied to the flash memory device. In a typical design, during tub erase 10 to 12 volts is applied to the tub, source and drain, and -6V is applied to the control gate of the flash memory device. However, in the state-of-the-art CMOS processes (usually used at a power supply voltage 3.3 V and below), it is difficult to build high voltage (HV) devices to support source/drain voltages of more than 6 volts unless the process complexity is significantly increased. Therefore, the required HV devices prevent tub erase from being widely used, especially for embedded applications.

Abstract: A mesh clock distribution system for reducing errors in synchronous systems caused by clock skew. The mesh clock distribution apparatus includes a mesh and a set of delivery conductors coupling a clock source to the mesh. Tile mesh is formed of a set of signal paths that interconnect at a set of nodes, wherein at least three of the interconnecting signal paths form the sides of a closed equilateral polygon. The set of delivery conductors transmit the clock signal to the nodes and the nodes distribute the clock signal along the length of the signal paths. Clocked elements in the synchronous system are connected to the signal paths and receive the clock signal from the signal paths.

Abstract: Methods and apparatus are disclosed for location of objects to facilitate retrieval, filing, security, inventory stock-keeping and the like. The methods and apparatus employ a tag element associated with each object-to-be-located, and interrogation system for searching one or more spatial regions for such tagged items, as well as mechanisms for identifying objects within the interrogated region.

Abstract: Digitized stereoscopic polarizing images of an object can be formed with a system containing a memory element, a data processor, and a printer for applying dichroic inks to molecularly oriented sheets. The memory element stores digital data representative of a left-eye image and a right-eye image of the object. The data processor can modify the digital representations of the left and right-eye images to enhance clarity, and orients the images for printing and stereoscopic alignment.