Abstract: The present application discloses methods to provide defect management, wear leveling and data security to a mass storage system implemented using flash memory. The flash memory is organized into a plurality of blocks. Each block has a special region for storing its attributes. In defect management, defects arising from manufacturing and on-the-fly defects are scanned. Defective blocks are marked by altering its attributes. The present application also discloses a wear leveling method in which the difference between the number of erasures of any two blocks (except the defective blocks) is within a predetermined value. The present application further discloses a new error detection and correction method. The same data is stored in two separate memory locations. The content of these two locations are later "ored" or "anded" together (depending on the nature of error giving rise to the error) to recover the correct data.

Abstract: A method is provided for sending data from a data source executing a network protocol such as the TCP/IP protocol stack, which includes a process for generating headers for packets according to the network protocol. The method includes sending such data on a network through a smart network interface. The network protocol defines a datagram in the data source, including generating a header template and supplying a data payload. The datagram is supplied to the network interface. At the network interface, a plurality of packets of data are generated from the datagram. The plurality of packets include respective headers, such as TCP/IP headers, based on the header template, and include respective segments of the data payload. The network interface supports packets having a pre-specified length, and the data payload is greater than the pre-specified length, such as two to forty times larger or more.

Abstract: An architecture for a mass storage system using flash memory is described. This architecture involves organizing the flash memory into a plurality of blocks. These blocks are then divided into several categories. One of the categories is a working category used to store data organized in accordance with a pre-defined addressing scheme (such as the logical block address used in Microsoft's operating system). The other category is a temporary buffer used to store data intended to be written to one of the working blocks. Another category contains blocks that need to be erased. When data is written into the mass storage system, a block in the second category is allocated from a block in the third category. The allocated block will then be changed to a block in the first category when writing to the allocated block is completed. The correspond block in the first category is placed into the third category. As a result, blocks can be recycled.

Abstract: An improved floating gate memory cell, having a dual thickness floating gate oxide, minimizes the band-to-band tunneling current and hot hole injection current suffered by the device, maximizes the Fowler-Nordheim tunneling current, allows lower operational voltages and provides a scalable structure. The process for manufacturing the dual thickness floating gate oxide structure comprises the steps of (1) forming a thicker insulator region over a channel region on the substrate, the thicker insulator having a source side and a drain side; (2) forming a thinner insulator on one or both of the source side and the drain side of the thicker insulator, and over a tunnel region in the substrate that is adjacent to the channel region; and (3) after forming the thinner insulator, distributing dopants in the source and the drain so that a concentration of dopants in the tunnel region beneath the thinner insulator is near or greater than a degenerately doped concentration.

Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.

Abstract: A redundancy architecture suitable for high density integrated circuit memory, such as mask ROM is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The memory used to characterize the failed row or column is implemented using an extra column or row respectively which is manufactured in a compact layout adjacent the array. Both an extra column and an extra row are laid out adjacent the array, using novel two transistor floating gate cells. Mode select logic is included by which replacement of a row or of a column is selected for the device. In the replacement row mode, a memory cell in the extra column is used to indicate the row to be replaced, and to enable the reading of the data from the replacement word line in place of the failed row.

Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.

Abstract: An architecture for an information appliance adapted for a specific application supports a variety of appliance personalities, relying on a single core technology. The information appliance comprises an application-optimized hardware platform, including a processor, a display coupled to the processor, an input/output device coupled to an information source and to the processor, a user input device, and working memory coupled to the processor. Non-volatile memory is coupled to the processor and stores appliance operating software and application software. The appliance operating software includes logic executed by the processor, which manages information flow from the information source through the working memory to the display, and the application software includes logic executed by the processor and responsive to the user input to manage selection of information from the information source.

Abstract: A redundancy architecture suitable for high density mask ROM integrated circuit memory is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The redundancy architecture can be manufactured using typical single metal, single polysilicon mask ROM processes. Redundancy cells are based upon a diffusion word line, a redundant word line adapted to replace a word line in the array and spaced away from the diffusion word line. First and second diffusion regions between the diffusion word line and the redundant word line, and a channel region between the first diffusion region and a second diffusion region form part of the redundant cell. A third diffusion region adjacent the redundant word line opposite the second diffusion region is arranged so that the second diffusion region acts as a source terminal, the third diffusion region acts as a drain terminal, and the redundant word line acts as a gate of a transistor.

Abstract: A method for forming a UV transmission passivation coating on an integrated circuit, such as EPROM, after completion of the active device and metal routing circuitry comprises depositing a first barrier dielectric layer over the integrated circuit; smoothing out underlying features by applying a layer of flowable dielectric over the first dielectric layer; and depositing a second dielectric layer over the flowable dielectric. Next a photoresist pattern is made over the second dielectric coating, having an opening layer over the at least one conductive pad. A wet etch process is used to remove portions of the second dielectric layer exposed by the opening. A dry etch process is used to remove portions of the remaining layers exposed through the opening, including the remaining portions of the second dielectric layer, the flowable dielectric layer and the first dielectric layer, down to the conductive pad. Finally, the photoresist is removed.

Abstract: A method for automated issuance of a coupon redeemable for goods or services purchased in a transaction involving a purchaser at a non-secure terminal on a public network is provided. The method includes receiving purchaser login data from the public network at a processing system, where the login data positively identifies the purchaser. The system provides through the public network to the identified purchaser a gateway to tools for selecting goods or services for purchase. The purchaser selects goods or services using these tools and provides payment information through the public network for the selected goods or services. The processing system verifies payment for goods or services. Next, the processing system generates coupon data, such as a clear text transcript of the transaction, and an encrypted transcript of the transaction. The coupon data is sent to the purchaser across the public network, enabling the purchaser to a coupon at a non-secure terminal.

Abstract: A low voltage supply circuit supplies an internal supply voltage in an integrated circuit, while consuming very little stand-by current, and providing substantial driving power to maintain the internal supply nodes at the desired voltage level. The low voltage supply circuit includes a first branch and a second branch. The first branch includes a pull-up circuit, a first transistor, a second transistor, and a reference circuit connected in series. The drain and the gate of the first transistor are connected to a first node. The pull-up circuit in the first branch is coupled between the first node and a power supply node. The drain and the gate of the second transistor are connected to a second node. The reference circuit is connected between the ground supply node of the integrated circuit and the second node, supplying a reference potential to the second node. The sources of the first and second transistors are coupled in common to a third node in the first branch.

Abstract: A thin silicon layer transistor integrated with a resistor. The resistor is self-aligned and contiguous with the transistor and is also formed of the same thin silicon layer as the transistor. This structure is particularly suitable for an SRAM circuit in order to simplify processing steps and to conserve area on SOS designs.

Abstract: An antenna for use at frequencies of 200 MHz and upwards has a cylindrical ceramic core with a relative dielectric constant of at least 5, and pairs of helical elements extending from a feed point at one end of the core to the rim of a conductive sleeve adjacent the other end of the core, the sleeve acting as a trap for isolating from ground currents circulating in the helical elements. To yield helical elements of different lengths, the sleeve rim follows a locus which deviates from a plane perpendicular to the core axis in that it describes a zig-zag path. The helical elements form simple helices with approximately balanced radiation resistances.

Abstract: A sequence of instructions for a processor executing a plurality of real time programs is supplied from a memory having a set of memory locations. A controller is coupled to the memory for replacing a program with a replacement program. The controller disables writes in response to instructions in the sequence from a particular group of memory locations with idle or no-operation instructions in response to a command. A memory interface is coupled to the memory and to the controller through which new instructions for the replacement program are written to the particular group of locations. The technique is applied especially for audio signal processors with a need for dynamic replacement of active voice programs.

Abstract: A satellite navigation receiver uses common dual-conversion superheterodyne and frequency synthesiser circuitry for receiving signals from both the GPS and the GLONASS satellite navigation systems. Successive first and second frequency down-converters in the receiver chain are fed by first and second local oscillator signals which are both variable in frequency such that the frequency of the first local oscillator signal is an integral multiple (preferably 8) of the second local oscillator signal. This relationship is provided by a binary divider (32) at least a portion of which may form part of a digital frequency synthesiser loop.

Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.

Abstract: A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list.

Abstract: A dual mode memory cell and integrated circuit is provided with a native mode and a ROM mode. ROM code implants are incorporated into a standard memory array. The implants are deep implants which do not have a large effect on the threshold of the cell under normal substrate bias conditions. However, as the substrate bias is increased, they have an increasing effect on the cell threshold. Thus, the cells in one embodiment are floating gate cells that can be read in a flash mode, in which the threshold of the cell is determined predominately by charge stored in the floating gate of the cell, and a read only mode during which a substrate bias is applied, the charge stored in the floating gates in the sector to be read are equalized, and the threshold of the cell is determined predominately by the ROM code implants.

Abstract: An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array.