Abstract: A sequence of instructions for a processor executing a plurality of real time programs is supplied from a memory having a set of memory locations. A controller is coupled to the memory for replacing a program with a replacement program. The controller disables writes in response to instructions in the sequence from a particular group of memory locations with idle or no-operation instructions in response to a command. A memory interface is coupled to the memory and to the controller through which new instructions for the replacement program are written to the particular group of locations. The technique is applied especially for audio signal processors with a need for dynamic replacement of active voice programs.

Abstract: A satellite navigation receiver uses common dual-conversion superheterodyne and frequency synthesiser circuitry for receiving signals from both the GPS and the GLONASS satellite navigation systems. Successive first and second frequency down-converters in the receiver chain are fed by first and second local oscillator signals which are both variable in frequency such that the frequency of the first local oscillator signal is an integral multiple (preferably 8) of the second local oscillator signal. This relationship is provided by a binary divider (32) at least a portion of which may form part of a digital frequency synthesiser loop.

Abstract: A communication technique for high volume connectionless-protocol, backbone communication links in distributed processing systems provides for control of latency and reliability of messages transmitted. The system provides for transmit list and receive list processes in the processors on the link. On the transmit side, a high priority command list and a normal priority command list are provided. In the message passing process, the command transmit function transmits commands across the backplane according to a queue priority rule that allows for control of transmit latency. Messages that require low latency are written into the high priority transmit list, while a majority of messages are written into the high throughput or normal priority transmit list. A receive filtering process in the receiving processor includes dispatch logic which dispatches messages either to a high priority receive list or a normal priority receive list.

Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.

Abstract: A dual mode memory cell and integrated circuit is provided with a native mode and a ROM mode. ROM code implants are incorporated into a standard memory array. The implants are deep implants which do not have a large effect on the threshold of the cell under normal substrate bias conditions. However, as the substrate bias is increased, they have an increasing effect on the cell threshold. Thus, the cells in one embodiment are floating gate cells that can be read in a flash mode, in which the threshold of the cell is determined predominately by charge stored in the floating gate of the cell, and a read only mode during which a substrate bias is applied, the charge stored in the floating gates in the sector to be read are equalized, and the threshold of the cell is determined predominately by the ROM code implants.

Abstract: An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array.

Abstract: A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.

Abstract: A cell portion 10 of a MOS structure and a redundant cell portion 12 of an MNOS structure are formed in a single semiconductor substrate. These MOS and MNOS structures commonly include an oxide film 26. A laminate structure consisting of a silicon nitride film and a pad oxide film and used in the element separation step is included in the redundant cell portion 12. Therefore, the redundant circuit can be naturally formed without increasing the number of process steps, leading to a high yield without inviting an increase in the manufacturing cost.

Abstract: The present invention provides method of encoding an electronic memory; multiple digital values are prioritized; respective digital values are associated with respective memory locations of the electronic memory such that there are multiple memory locations each associated with two or more different digital values; and respective digital values are loaded into respective memory locations of the electronic memory in order from lowest priority digital value to highest priority digital value wherein each respective digital value is loaded into all respective memory locations that are associated with such respective digital value.

Abstract: A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure.

Abstract: A communication server includes one or more ISDN ports or other wide area network ports, one or more local area network ports, a plurality of processors and data channel resources which execute a process for distributing data channel signal processing among the plurality of processors.

Abstract: A bus protocol technique removes the transaction used for posting indications of events to the host processor from the bus. The invention takes advantage of the fact that addresses typically on a high speed bus contain fewer bits than the entire bus width. Particularly, for a 32 bit bus, the 32 bit address space is not always necessary. The remaining bits on the bus are used for an encoded event tag. A bus transaction involves a first bus transfer which provides an address for writing or reading data, along with the event tag. The event tag is detected and decoded by the destination, and the event is posted to the processor which monitors and responds to events, in a manner which is synchronous with completion of the transaction. Thus, after the transaction on the bus, the message subject of the transaction is waiting in the memory, and notification of the event has occurred automatically and synchronously with completion of the transfer.

Abstract: A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.

Abstract: A router includes synchronous dynamic random access memory (SDRAM) based shared memory, with a controller configured to control the order in which the SDRAM access is granted to a plurality of interfaced components. In one embodiment, the controller's configuration minimizes the amount of time data from a particular source must wait to be read to and written from the SDRAM, and thus minimizes latency. In a different embodiment, the controller's configuration maximizes the amount of data read to and written from said SDRAM in a given amount of time and thus maximizes bandwidth. In yet another embodiment, characteristics of the latency minimization embodiment and the bandwidth maximization embodiment are combined to create a hybrid configuration.

Abstract: Traffic involved in maintaining a set of connection oriented sessions between end stations in a network is managed to optimize and reduce the polling traffic needed to maintain the connection oriented sessions across a common link between edge devices. At a first edge device, a member of a set of connection oriented sessions is selected as a polling session. Request polling traffic of that polling session is forwarded from a first edge device to the second edge device. All other polling traffic from other members of the set of connection oriented sessions is blocked at the first edge device. The set of connection oriented sessions is maintained in response to polling traffic of the selected polling session. A similar algorithm is executed at the second edge device to manage the traffic in both directions across the common link.

Abstract: A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry.

Abstract: The sense amplifier of the present invention contains a circuit that can pre-charge its output to a default state (e.g., the "0" state) during one time period and sets the output to a second state in another time period only if there is a need to do so. In this sense amplifier, cell leakage (and not cell current) is used as reference. Further, only the second state needs to be developed. As a result, the sensing margin increases. One characteristics of the present sense amplifier is that different parts of the circuit is active during different time period. As a result, both noise and power consumption is reduced. The sense amplifier is coupled to a timing circuit that can provide appropriate timing signals to operate the sense amplifier. In addition, a power-on reset circuit is disclosed. This reset circuit is operative when power is first applied to the system. It causes the timing circuit to generates a timing signal so that valid data can be detected by the sense amplifier when power is turned on.

Abstract: A scalable CSMA/CD repeater is based on polling and collision resolution logic, and slot time and interframe gap negotiation logic controlled by the repeater itself. The repeater based polling and collision resolution provides central control of the backoff and retry algorithm of each connected MAC unit. Thus, the MAC unit does not rely on random backoff mechanisms that significantly degrade performance of prior art systems. Furthermore, the retry by a MAC unit after a collision is managed by commands received from the collision resolution logic in the repeater. The repeater based collision resolution logic ensures that all ports involved in a collision have a fair opportunity to forward a packet without being blocked before enabling all the ports in the network to freely compete again.

Abstract: Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.