Abstract: A programmable on-focal plane signal processor having analog to digital conversion, nonuniformity correction, gamma spike compensation all digitally performed on a single silicon substrate inside a dewar. The architecture supports time delay integration and spatial filtering to increase the signal to noise ratio of the focal plane array data. The processor has programmable coefficients which may be changed while the system is operating or eliminated. The architecture provides increased signal noise ratio for infrared data and decreases the output data bandwidth from the infrared focal plane array by two orders of magnitude.

Abstract: An Asynchronous Communications Interface to Synchronous Circuit having three stages is disclosed. The first stage captures the control and data signals from an asynchronous bus and converts them into signals which are synchronous to the internal clocks of the interface chip. The second stage of the interface is a synchronous state machine which utilizes the synchronized signals generated by the first stage to determine the current state of the asynchronous bus. The third stage of the interface uses the data generated by the synchronous state machine and the control and data signal capture logic to validate the data in a synchronous manner. This allows further processing of the data from the asynchronous bus without the use of any further asynchronous logic or timing.

Abstract: A programmable hardware adapter for switching between two or more levels of arbitration priority for devices connected to a communications bus without host processor intervention. The adapter is programmed with an external arbitration value at initial program load. A control bit selects whether the arbitration level within the adapter is used for arbitration or if the device's internal arbitration level is used. When the external arbitration level is used to vie for the bus, the adapter's state machine sends a signal to the device to tell it it won or lost, depending on the outcome of the arbitration.

Abstract: A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus.

Abstract: A Time Reference Manager for providing a time reference value to the nodes of a ring topology local area network. A time reference is implemented on a distributed system data bus at a low level interface to provide highly accurate time reference values at each node of the LAN with no settling time required. One node on the network is designated as the Time Reference Manager and broadcasts the Time Reference Protocol data around the ring of the LAN network. Time delay correction is provided by an algorithm performed in a time reference software process. Clock accuracy is selectable by the number of bits used in the clock-counter.

Abstract: A Micro Channel integrated circuit design capable of controlling high speed data and control transfers between a Micro Channel bus, a local processor, and a dedicated local data bus. The interface controller utilizes enhanced features of the Micro Channel and data buffering to achieve high speed data communications with various bit size Micro Channel devices. Queued commands are handled by flexibly programming the interface control operations. Interface control hardware increases the processing speed of data transfers by implementing performance critical functions of queuing in hardware. Extensive error checking and reporting and self-test give the interface controller advance functions as an input/output processor.

Abstract: A method and apparatus for cooling thermally massive parts includes directing a chilled gas onto an electrical component travelling on the belt of a continuous furnace. The belt is divided into a series of hot and cold zones to provide thermal stressing to the electrical component to detect early life failure. As the component cools, a constant thermal stress is maintained by either lowering the temperature or increasing the flow rate of the chilled gas.

Abstract: A self-tuning and efficient computer method is disclosed for the management of virtual storage applicable to dedicated real-time computer systems. This method interposes a layer between the application and the real-time computer system to form a two-layered structure to meet an application's request for virtual storage (i.e. buffer request). The method adds a real-time system's slower allocation (second layer) to guarantee the creation of all other buffers during one real-time period. The self-tuning first layer is checked first to satisfy a buffer request, while the untuned second layer is entered to create a buffer when the first layer fails; either the request size is not yet tuned, or the pre-allocated buffers have run out. These entrances to the second layer provide a monitoring mechanism from which a new pre-allocation definition, based on the system usage history, is derived to tune the first layer at the next initialization time.

Abstract: A method and apparatus for processing a digital signal by a fast Fourier transformation using balanced coefficients. The balanced coefficient method reduces the number of coefficients required to process an FFT of size 2.sup.p from a total of 2.sup.p coefficients to p times the square root of 2.sup.p. The new system employs a reduced number of coefficients in a unique addressing scheme to produce a cheaper, lighter, smaller, cooler FFT processor which uses less power and is more reliable.

Abstract: An apparatus for injecting errors into a FDDI token ring network is disclosed. The error injection scheme operates by fooling a FORMAC into thinking it sent a real frame of data. This is done by using two RAM buffers. The RAM buffer normally accessed by the RBC/DPC becomes a SHADOW RAM during error injection operation. A dummy frame is loaded into the shadow RAM in order to fool the FORMAC. This data is just like the data that would be used if sending a normal frame, with the restriction that it must be shorter than the error injection data. The other buffer, the error injection RAM, contains the error injection frame. The error injection data is sent out to the media by switching a multiplexor. When the FORMAC is done transmitting the data, the multiplexor is switched back to the normal mode. Thus, the FORMAC is unaware of what happened and the token ring remains operational.

Abstract: A method of forming a radiation hardened SOI structure is disclosed. The buried oxide layer of an SOI structure is hardened prior to the bonding of a device wafer which forms the silicon portion of the silicon-on-insulator. The radiation hardening is done by implantation of recombination center-generating impurities. All the radiation hardening is done prior to the bonding of the device silicon layer and allows for radiation hardening of the buried oxide layer of an SOI structure without any damage to the silicon device layer.

Abstract: A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.

Abstract: Disclosed is a system and method for providing a reuser of a software reuse library with an indication of whether or not a software component from the reuse library is authentic and whether or not the software component has been modified. The system and method disclosed provides a reuser with assurance that the software component retrieved was placed in the reuse library by the original publisher and has not modified by a third party. The system and method disclosed uses a hybrid cryptographic technique that combines a conventional or private key algorithm with a public key algorithm.

Abstract: A method of having a frontside contact to a SOI wafer is described. Before any device processing steps a trench is etched through the SOI layers to the substrate. This trench is maintained during device processing and opened during source/drain implantation. At metallization an ohmic contact is made to the substrate.

Abstract: A method for the transferring of 3 phase, asynchronous AC power between a present source supplying power to a load and an alternative source to supply power to the load. The maximum phase displacement is 60 electrical degrees at the load. The transfer can occur between sources which are rotating "forward" or "backward" with respect to each other or jointly with respect to the load. Either present source, alternate source or the load may be used as the timing reference for determining best phase connection of the alternate source to the load.

Abstract: A distributed arbitration scheme for a communications bus wherein the bus interface modules decide among themselves who should next use the bus. The protocol is a common multiprocessor backplane bus interface for supporting multiprocessing, shared memory, and memory mapped input/output operations. The protocol allows programmable priority which can be changed during system operation. The architecture handles interrupts over the bus and therefore eliminates separate interrupt lines. The scheme can implemented in CMOS technology and is compatible with other integrate circuit device technology.

Abstract: A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.

Abstract: Many sensor information processing applications currently use monochrome B-scan presentations to exhibit processing results from radar, sonar, spectral estimation, seismic profiling, radio astronomy, bio-engineering, and infrared imaging. The use of color for such raster display presentations have been limited to the coding of amplitude values for a fixed set of hue/luminance colors to convey recognition by the human operator. Hue and luminance are used here independently to convey two orthogonal pieces of low signal-to-noise sensor information simultaneously to the operator for quick and accurate recognition. The net result is an added degree of freedom available on a single display surface, which not only improves operator recognition and reaction time for critical events, but precludes the necessity of a second display presentation for the alternate information and subsequent correlation of two data sets by visual comparison.

Abstract: A method of replicating changes made to databases distributed throughout a computer network is described. A first program (TP1) in the Collector node instructs a second program (TP2) in the Collectee node to send all updates to a database since the last conversation. TP2 processes queries to retrieve any changes made since the last conversation between the Collector and Collectee nodes and send the data to TP1, which updates the copy of the database on its own system.

Abstract: The resolution of two asynchronous three-phase power sources such that an optimal phase to phase matchup may be made between them. This is achieved with a logic system that receives a data point at the zero-voltage crossings of the three waveforms from each source. The data points create distinct "states" of the three-phase waveform for each power source. There are six data points for each power source per cycle. The states of the load and source, along with information pertaining to the connection configuration of the present source of power to the load, are used to determine the optimum configuration for connecting an alternate or new source to the load based on information obtained from a lookup table.