Abstract: A hybrid probe card and methods are provided. A plurality of uniform sized probe pins are provided in a probe card for performing wafer probe testing. The probe card also includes at least one enlarged probe pin having a current carrying capacity that is at least 25% greater than the current carrying capacity of the uniform sized probe pins. The enlarged probe pins are provided, e.g., to prevent damage to the probe pins caused by large current flow. Methods for identifying the probe pin locations where the enlarged probe pins should be deployed are described.

Abstract: A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.

Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

Abstract: An integrated circuit package (30, 32) for vertical attachment as part of a high density module (200) having a carrier (70) having an opening (86), routing strips (82), conduits (84) and side surface terminals (100), the side surface terminals (100) disposed on a side surface (92), which side surface is common to the carrier (70) and the integrated circuit package 30, 32. An adhesive layer (60), which attaches a silicon chip (50) to a carrier (70), wire bonding (80) electrically connecting the silicon chip (50) to the routing strips (82) and potting material (90) filling the opening (86), are also disclosed.

Abstract: A high density unit (130, 160) comprising a first integrated circuit package (30, 32) comprising a carrier (70) having first and second sides (92, 94), a silicon chip (50) attached by an adhesive layer (60) and solder bonding (80) electrically connecting the silicon chip (50) to the carrier (70) stackably and electrically connected to a second integrated circuit package (30, 32), is disclosed.

Abstract: A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.

Abstract: A circuit (10) operates at relatively low values of the supply voltage, and includes a differential input circuit (16) which receives a differential input signal at first and second terminals (18, 21). A differential voltage derived by the input circuit from the differential input signal is present at third and fourth terminals (28, 31) and is amplified by a differential amplifier (12). A differential level adjuster (14) adjusts output voltages from the amplifier to suitable values for application to a matcher (15). The matcher (15) generates two currents that also flow within a differential compensator (17), and that match respective currents flowing in the amplifier. The differential compensator then provides a suitable current to each of the third and fourth terminals, such that the current flow between the first and third terminals, and between the second and fourth terminals, is substantially zero.

Abstract: Analog to digital conversion circuitry (800) is disclosed, comprising multiple quantization circuits (802), having a quantization resistor (814, 816, 818, 820) coupled between inputs of adjacent quantization circuits, wherein each quantization circuit comprises an input source follower circuit (804) having an input coupled to an analog voltage input and an output, an output source follower circuit (812) having an input and an output coupled to a digital voltage output (822, 824, 826, 828), a base transistor (836) having a first terminal coupled to the output of said input source follower circuit, a reset transistor circuit (806) coupled to said first terminal and adapted to selectively ground said first terminal responsive to an external signal, a resonant tunneling diode structure (810) coupled at a first end to a second terminal of said base transistor and at a second end to ground, and a dynamic hysteresis loading circuit (808) coupled to a third terminal of said base transistor and to the input of said ou

Abstract: There is disclosed a system and method of providing electrical isolation between a telephone line and a connected device, such as a computer. In one embodiment the telephone line is 2-wire and the connected device is 4-wire and includes a feedback elimination circuit. A pair of controlled CTR opto diodes are used in the communication path to effect electrical isolation. The opto diodes are used in conjunction with an electronic inductor constructed using a pair of cascoded darlington transistors to control the telephone line voltage and current and the circuit is designed to maintain the optocouplers within their linear operating range.

Abstract: A method and apparatus for compensating for input threshold variations in input buffers is provided. The method and apparatus compensate for input threshold variations by applying a bias voltage on a known capacitance of an RC calibration circuit using, for example, a pulse width modulator. The bias voltage helps ensure that the time to charge the known capacitance from the bias voltage to the input threshold voltage of the input buffer is independent of the threshold voltage. The bias voltage is chosen using an iterative process in which the time to charge from the bias voltage to the threshold voltage is compared with a reference time. The bias voltage is adjusted based on the comparison.

Abstract: An apparatus and method for detecting defects on silicon dies on a silicon wafer (16) comprising an image acquisition system (10) and a computer (32) that determines a statistical die model by analyzing a random selection of dies (42) within a die matrix (37) and compares the statistical die model to matrices of silicon dies (38) to determine which silicon dies (38) have surface defects, is disclosed.

Abstract: This application describes a method of protecting data and program code stored in an EPROM array from piracy. The security scheme allows for segmentation of the array to protect one section of the array from reading while programming a non-secure section. The security scheme also allows for protection of the entire array after programming is complete. It also incorporates a device to prevent tampering with the segmentation registers and a means to prevent circumvention of the security scheme even when the processor is in one or more of its test modes.

Abstract: A DC to DC power converter (58) and method of controlling the DC to DC power converter (58). The converter (58) has a first switch (S.sub.1) coupled to a second switch (S.sub.2). The converter (58) is adapted to receive an input voltage V.sub.in, generate an output voltage V.sub.out, and operate at a switching frequency. A hysteretic mode control circuit (52) includes a first circuit generating a ramp signal at input (56) for controlling the converter (58). The first circuit includes a first capacitor (C.sub.1) with the ramp signal generated at an end of the first capacitor (C.sub.1). The hysteretic mode control circuit (52) is coupled to the first (S.sub.1) and second (S.sub.2) switches, where the switching frequency of the first and second switches is dependent upon the ramp signal (56) determined by the value of the components of the first circuit rather than on the voltage from the output filter of the DC to DC power converter.

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A plastic packaged integrated circuit (20) having a thick copper plated top surface level interconnection structure. A semiconductor integrated circuit (20) is formed having devices at the surface of a semiconductor substrate (23). First and second metallization layers (27, 31) are formed over the substrate and contacting selected ones of said devices. The first and second levels of metallization may be in contact with one another through vias. A thick top surface level metal interconnect layer (35) is then formed over the second metal layer (31), either physically contacting it or selectively electrically contacting it. The surface level metal (35) is fabricated of a highly conductive copper layer. The thick surface level metal layer (35) substantially lowers the resistance of the interconnect metallization of the device (20) and further eliminates current debiasing and early failure location problems experienced with integrated circuits of the prior art.

Abstract: A circuit (12) for reducing positive ground bounce effects on an integrated circuit (10) of the type having an integrated circuit transistor (40) that has reduced conduction when exposed to a positive ground bounce potential includes circuitry responsive to an increase in ground potential to produce a drive current and circuitry for applying the drive current to the integrated circuit transistor (40) to oppose the reduced conduction. The positive ground bounce circuit (12) has a ground bounce sense transistor (56) of same conductivity type as the integrated circuit transistor (40), and a circuit (69) to bias the ground bounce sense transistor (56) normally into conduction to pass a control current. Since ground bounce sense transistor (56) also has reduced conduction when exposed to a positive ground bounce potential, a diode (72) is provided to redirect the control current to the integrated circuit transistor (40), thereby reducing the effects of a positive ground bounce condition.

Abstract: An isolation circuit (10) and method for providing dc isolation between two integrated circuit devices (11) and (12) that may be referenced to different ground potentials is presented. The isolation circuit (10) includes, in each circuit, an output buffer (20, 20') connected to deliver a signal to an input/output pin (16, 17) of the circuit (11, 12) with which the output buffer is associated. A capacitance (30), which may be a single capacitor or a combination of capacitors, is connected to the pins (16, 17) of each of the circuits (11, 12), and in each circuit (11, 12), an input buffer (22, 22') is connected to receive a signal delivered onto the I/O pin (16, 17). The input buffer (22, 22') includes a circuit for resisting a charge leakage from the capacitor, which, preferably is a bus holder circuit (36), or the like. In another embodiment, a transformer (85) is used to provide dc isolation between the two integrated circuits (62, 64).

Abstract: A driver circuit (12) having a reduced propagation delay is provided. The driver circuit (12) includes a first device (56) having an input and operable to switch a supply voltage to a load (14). A second device (54) having an output coupled to the input of the first device (56), operable to turn on the first device upon receipt of a first signal. A third device (66) having an output coupled to the input of the first device (56), operable to turn off the first device upon receipt of a second signal. A kick start circuit (30) coupled to the input for the first device (56), the input for the second device (54), and the input for the third device (66), operable to generate a threshold voltage on the first device (56), the second device (54), and the third device (66). The kick start circuit (30) operable to produce a threshold voltage that is just below the voltage in which the first device (56), the second device (54), and the third device (66) turn on, or conduct.

Abstract: A method and apparatus for nondestructive inspection of packaged integrated circuits and defect detection in the integrated circuits. In a scanning acoustic microscopy system, a packaged integrated circuit under test 31 is placed in a tank containing an acoustic transmission medium such as de-ionized water. An acoustic reflector 29 is placed beneath the integrated circuit 31. A pulse-echo mode transducer 17 is used to scan the area containing the integrated circuit 31 with ultrasonic energy. The reflective signal energy is captured by the transducer 17 and the signals are digitized and stored. A computer system analyzes the reflective signal amplitude, and presents a visual image based on where the reflective signal was strong and where it was weak. In a preferred embodiment the image is presented so that the signal from the reflective plate is shown as a dark region where the reflection was weak or zero.

Abstract: The invention is a circuit for converting a voltage which is the difference between a supply voltage voltage V.sub.cc and input voltage V.sub.in, to a voltage which is the difference between an output voltage V.sub.out and a reference Gnd, comprising. A first resistor R.sub.1 for producing a voltage V.sub.In-mirror is used in conjunction with V.sub.cc. V.sub.In-mirror is a mirror value of V.sub.in. A second resistor R.sub.2 is used, across which, the output or concerted voltage V.sub.out is produced. A first mirror circuit cascoded with a second mirror circuit, is connected between the first resistor R.sub.1 and the second resistor R.sub.2 for producing currents in the first and second resistors to provide output voltage V.sub.out across R.sub.2.