Abstract: An integrated circuit fabrication technique for constructing field isolation structure components and subposing electrical barrier isolation region components in a substrate is disclosed. A nitride-less mask is used to pattern a major surface of the substrate with apertures where the isolation barrier components are to be implanted. Following the formation of the isolation components, a thick oxide is formed on the substrate, masked, and etched to form field oxide structures on the major surface of the substrate. Bird beaks, bird crests, crystalline dislocations and white ribbon problems associated with nitride masking processes are virtually eliminated.

Abstract: A single component electrically erasable memory cell is disclosed. A floating gate MOSFET having a relatively short channel is triggered into a snap-back mode positive feedback biasing mechanism. Hot-hole injection onto the floating gate during the snap-back mode neutralizes any charge stored there to represent a data bit.