Abstract: A method and system for identifying inhibited interrupts in a processor system, the processor system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes initializing the at least one PMC and counting a number of cycles or occurrences with the at least one PMC that exceptions are ignored during a predetermined sampling period. In a second aspect the method and system provides for initializing at least one PMC and counting a number of cycles or occurrences with the at least one PMC that an interrupt is pending during the predetermined sampling period. The counted number of cycles/occurrences assists in identifying potential areas of improving system performance in order to reduce the counted values.

Abstract: A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.