Abstract: This invention relates generally to medical devices, and more particularly, an apparatus and method for collecting cells or tissue samples from the cervix of a patient for medical testing.

Abstract: Arrangements are disclosed for use in a network of digital data processing systems for rapidly encoding information signals for transmission over communication links in the network, and for rapidly decoding information received thereover, thereby to facilitate higher-bandwidth communications over the network. In addition, network command and control information transmitted along in the data transmitted over the network is rapidly decoded and verified by a command decoder and command verifier.

Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives and stores the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's storage subsystem receives and stores the generated information from control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module.

Abstract: A digital data storage subsystem stores data for use by digital data utilization device. The data as used by the digital data utilization device being organized in the form of variable-length records. The digital data storage subsystem includes a digital data storage device, a cache and a cache control. The digital data storage device has at least one fixed block storage unit for storing a predetermined amount of data, the storage unit storing at least one record and additional padding if the record does not comprise at least said predetermined amount of data. The cache including at least one cache slot which can accommodate the storage of the predetermined amount of data, that is, the amount which can be stored on the block storage unit of the digital data storage device.

Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module. The filter/buffer module filters and buffers the information received from the mass storage subsystem and provides the buffered information to the tape log module for storage.

Abstract: A computer system for connection in a network, which has a number of other devices each of which may receive communications from the computer system. The computer system includes a network interface and a message transmission control circuit. The network interface establishes a communications session with a selected one of the other devices as a destination for transmitting messages to the selected device. The message transmission control circuit enables the network interface to establish a communications session and transmit messages thereover with the selected device. The message transmission control circuit initially enables the network interface to transmit a number of messages corresponding to a log-in credit value selected for the selected device. Thereafter, the message transmission control circuit enables the network interface to transmit message based on flow control information received from the selected device.

Abstract: A method and apparatus are for maintaining a cyclic redundancy check (CRC) byte is described which eliminates additional input/output (I/O) transactions for the case when a write to a partial sector is required while the CRC byte is maintained for an entire sector. The method includes performing an XOR operation between the partial write data and the data it is to displace, and then performing an XOR operation between the old CRC byte associated with the sector and the result of the XOR operation between the partial write data and the data it is to displace.

Abstract: A storage and retrieval system for a plurality of data storage media includes a 3-dimensional data storage media storage cabinet having a plurality of moveable data storage media storage locations, at least one of which is empty or unused. Each data storage media storage location is moveable along at least two orthogonal axes, to facilitate retrieval of a selected one data storage media. Each data storage media is indexed in a data storage media system controller. When access to a predetermined one data storage media is requested by a command or request from a data processing system such as a host computer, the data storage media system controller, utilizing the index, determines the media transport control signals required to effectuate the quickest access to the media. A retrieval mechanism retrieves the media from a retrieval region in the storage cabinet and places the media into and out of a read/write mechanism, to allow access to the data storage media.

Abstract: A dual bus architecture for a computer system including a number of computer system devices and a number of computer system resources. Each of the computer system devices and computer system resources are coupled by first and second communication busses. First and second bus arbitrators provide bus arbitration functions allowing first and second computer system devices to access first and second computer system resources simultaneously. A method of accessing a number of computer system resources by a number of computer system devices coupled by a dual bus architecture is also provided.

Abstract: A network includes a plurality of computer systems interconnected by a plurality of communication links. At least one of the computer systems includes a resettable computer and a reset circuit. The reset circuit is actuable in response to the receipt of a message containing a received reset code value for generating an interrupt signal and to begin a timing interval, and at the end of said timing interval to generate a reset signal. If the computer is in its normal operational condition, it is responsive to the interrupt signal from the reset circuit to deactuate the reset circuit prior to the end of the time interval to prevent the reset circuit from generating the reset signal. On the other hand, if the computer is in the hung condition, it does not respond to the interrupt signal, and so the reset circuit at the end of the time interval will generate the reset signal to enable the computer to initiate a reset operation.

Abstract: First and second pairs of pins and cooperative first and second pairs of pin receiving apertures are provided at the confronting connector faces of each of one or more data storage device carrier subassemblies and an interconnection board of a storage system card cage subassembly into which each data storage device carrier subassembly is slidably mounted. The first pin/aperture pair engage and cooperate first to prealign, mechanically support and vibrationally damp each data storage device carrier subassembly.

Abstract: An apparatus which provides a high data transfer rate to and from an asynchronous bus. The apparatus includes a synchronous logic network to provide a transaction connection between the asynchronous bus and the data transfer device during an initial phase of the transaction when many determinations are required and an asynchronous logic network to provide data transfer between the asynchronous bus and the data transfer device during a subsequent phase of the transaction when very few determinations are required.

Abstract: A pipelined, microcoded CPU employs conditional branching in microcode execution Data path conditions produced by one microinstruction are used in the selection of a following microinstruction. In high-performance systems, multiple cycle microbranch latency requires that the generation of microbranch conditions be pipelined. Usually a microbranch condition is used exactly once, at the earliest possible time, when dynamic microbranch conditions are only valid a fixed number of microinstructions later in the pipeline. Flexibility of the microcode algorithm is increased by selectively inhibiting the update of the dynamic conditions to delay the use of the condition by one or more cycles, under microcode control, thereby implementing dynamic microbranches, while allowing use of previous dynamic microbranch state.

Abstract: Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly.

Abstract: A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

Abstract: A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.

Abstract: A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.

Abstract: A transmitting node generates error correction symbols by encoding data using error correction code integrated with information which identifies the data cycle in which the data are to be transmitted, the integrated encoded data having the same number of bits as the error correction code has alone. A node receiving the data generates error correction symbols encoding the received data using error correction code integrated with information which identifies the data cycle in which the receiving node is operating. A comparison is made of the transmitting node error correction symbols received with the receiving node generated error correction symbols, and if the two sets of symbols do not match, the receiving node detects and, if possible, corrects errors in the data using the error correction code. Alternatively, the receiving node may remove the data cycle information from the received error correction symbols and perform a comparison using standard error correction code applied to the received data.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus.