Abstract: The virtual graphics processor is a software process that enables different video display systems to execute the same graphical display application. The process also permits the display application to be updated or reconfigured in real time without changing the embedded display system software. The parts of the virtual graphics processor include an application graphics database for storing graphic primitives and associated static primitive data defining one or more graphic pages in a display application. An image control interface (video library) associates graphic functions of the particular video display system with graphic primitives in a requested page. An instruction sequencer within the virtual graphics processor responds to a display request by obtaining the requested graphic page from the graphics database and associated graphics functions from the video library.

Abstract: An interface to internal scan paths within an IC for synchronizing a test clock and a system clock without adversely affecting their operation. The test clock provides input test data (TDI) to the interface and receives output test data (TDO) from the interface at the test clock rate. The system clock drives the test data through the scan path at the system clock rate. The two clocks are "decoupled" in that they run independently, being synchronized by the interface for clocking the test data into, through and out of the scan path. In effect, the interface decouples the internal scan paths driven by the system clock from the test logic driven by the test clock. This feature enables the IC to be tested "at speed" and provides for synchronization between the test clock and system clock over a wide range of test clock frequencies.

Abstract: This invention is a circuit for a vehicle which will enable the engine to run, and the heater or air conditioner to operate without the key in the ignition switch by supplying power to the ignition and acessory circuits. The operation starts the vehicle, presses a switch, then removes the key. Now the engine is idling, and the heater or air condition will work, but the vehicle cannot be driven. The circuit automatically shuts off if the vehicle is put into gear. It also shuts off if the vehicle's engine overheats, or looses oil pressure. The vehicle may be driven by reinserting the key into the ignition switch and turning it to the "ON" position. The starter is disabled while the circuit is enabled, in case the operator turns the ignition switch to "START" while turning it to the "ON" position. This prevents damage to the starter and flywheel. The circuit can only be energized while the vehicle's engine is running.

Abstract: A digital trigger for a digitizing instrument having multiple analog-to-digital converters employed in interleaved fashion and in which the clock phase and period of a trigger point can be accurately determined. The digital trigger includes a digital comparator for comparing the output signals of each analog-to-digital converter to a trigger threshold level to generate a trigger signal at the output of the comparator if a trigger point occurs on the output signal. The outputs of the collective digital comparators are routed to decoding logic which generates a digital signal that indicates the phase of the clock period in which the trigger point occurred. The outputs of collective digital comparators are also logically ORed together for detecting if a trigger point occurred during a clock period.

Abstract: A voltage controlled oscillator with temperature compensation and reduced trigger jitter. The temperature compensation is improved by applying an on-chip generated temperature-dependent control voltage to first and second parallel oscillator stages through which the oscillation signal passes. The second stage has a greater signal propagation delay than the first stage. The control voltage determines the signal delay contributed by each stage to the oscillating signal, decreasing the delay in response to a temperature-induced decrease in oscillator frequency and increasing the delay in response to a temperature-induced increase in frequency. The oscillator also includes means for generating oscillations from a predetermined signal phase that is independent of the oscillator phase before triggering.

Abstract: A memory pointer circuit includes a plurality of counters and a programmable logic array for controlling the counters to generate addresses for an acquisition memory. The programmable logic array directs a lower counter to generate a repeating sequence of addresses to store data before an event occurs, each pass through the sequence causing previously written data to be overwritten until an event has occurred and is stored in memory. The programmable logic array then directs the upper counters to increment and the lower counter to generate a following sequence of addresses to store data after the event occurs. Once the following sequence is complete, the upper counters are again incremented and the repeating sequence of addresses is again generated. The procedure is repeated to store multiple clusters of data and events in the acquisition memory. Once the acquisition memory is full, the stored data and events can be saved or overwritten.

Abstract: A digital-to-analog converter filter circuit includes a means for generating a blanking signal to coincide with a change in the digital signal value to the converter and an analog switch controlled by the blanking signal. The analog switch receives the analog signal from the converter and passes the signal depending on the state of the blanking signal. The blanking signal controls the switch to block passage of the analog signal for a predetermined time sufficient for the analog signal to settle after transition from a first value to a second value in response to the change in the digital input signal value. The analog switch is connected to a vector filter which receives the analog signal and transmits a delayed transition signal from the first analog signal value signal to the second value. The filter transmits the first value until the switch passes the second value upon command of the blanking signal.

Abstract: A trigger circuit for detecting plural simultaneous input signals and generating a trigger signal in response thereto includes a word recognizer and a state machine. The word recognizer reconstructs eacg input signal in response to predetermined high and low threshold voltage logic levels and the input signal. The reconstructed signals indicate the input signal's logic level above the high threshold level, below the low threshold level, and transitionally between the high and low logic levels. The trigger circuit provides both clock-based and time-based trigger modes. The clock-based trigger modes include single event triggering, nested event triggering, and consecutive and exception event triggering. The time-based trigger modes include these modes and in addition setup and hold-time triggering, transition time triggering, and sliver pulse triggering.

Abstract: An adjustable delay element for digital systems includes a high-pass filter in parallel with a low-pass filter. The high-pass filter passes the higher frequency component of the digital signal and the low-pass filter passes the lower frequency component to introduce a delay into the digital signal. A current multiplier directs a selectable portion of the higher frequency component to aid or oppose the lower frequency component to vary the delay within the signal. An output stage receives the lower frequency component with the selected portion of the higher frequency component and reproduces the digital signal with the delay. Embodiments for both differential and single-ended versions of the corresponding delay element are disclosed.

Abstract: A method of measuring automatically the peak-to-peak amplitude of electrical input signal utilizes both trigger circuits of a dual trigger oscilloscope. The steps of the method include adjusting automatically the trigger level of the first trigger circuit until the first trigger level is equal to the maximum peak of the input signal while adjusting automatically the trigger level of the second trigger circuit until that level is equal to the minimum peak of the signal. The second level is then subtracted from the first level to calculate the amplitude. To minimize the time involved, the method distinguishes between signals faster than and slower than a preselected frequency and calculates more rapidly the amplitude for faster signals. Time is also minimized by adjusting hysteresis levels and voltage level settling times as the trigger levels are increased and decreased in search of the peak signal values.

Abstract: An analog signal multiplexer for differential signals comprises a plurality of channels, each channel having a pair of differential amplifiers forming an input stage for receiving a differential input signal and a pair of output transistors for forming an output stage producing a differential output signal. Each differential amplifier has a pair of emitter-coupled transistors, with each transistor having an additional emitter cross-coupled to the additional emitter of the opposite transistor of the other emitter-coupled pair. A plurality of current sources are provided to bias the emitter-coupled and emitter cross-coupled pairs. By selectively enabling the current sources, the input signals forming the differential input signal can be applied with normal polarity or inverted polarity to a respective transistor of the output stage to produce a normal or inverted differential output signal or to both transistors of the output stage to produce no differential output signal.

Abstract: A differential to a single-ended converter circuit includes linearizing PN junctions that compensate for input signal voltage loss in the input stage. A variable voltage source and a resistor are provided for adjusting the voltage produced across these junctions by varying the current through these junctions. The converter circuit also includes a shunt feedback amplifier for inverting half the differential output voltage so that it sums with the differential voltage of opposite phase to produce the single-ended output signal. The shunt feedback amplifier is operated at a constant current to minimize error voltages. Bootstrapping is employed to linearize thermal distortion of the PN junctions and means are provided for compensating for the resulting thermal distortion.

Abstract: A method and apparatus for automatically calibrating the deflection of an electron beam in a graticuled cathode ray tube. The apparatus includes a microprocessor and digital-to-analog converter for generating input signals of a predetermined accuracy and sending the signals to an amplifier of a cathode ray tube to deflect the electron beam across graticule lines on the faceplate. A phototransistor optically coupled to the faceplate detects the electron beam coinciding with the graticule and in response generates an electrical signal. Signal processing circuitry processes the signal to remove noise from it and retrieve detection signals. The microprocessor receives the detection signals from the signal processing circuitry, compares each detection signal to its corresponding input signal, and adjusts the gain and offset of the amplifier in response to the comparison. Additional circuitry digitally records the beam position relative to the graticule lines.

Abstract: A resonance compensated unity voltage gain amplifier comprises an input stage and an output stage connected in feedback to the input stage and a series resonance circuit for compensating for the resonance of the output and input stages created by the feedback. Reactance of the series resonance circuit is adjusted to be substantially zero at the resonant frequency of the amplifier. The resonance compensated amplifier is incorporated into a gain selectable amplifier. The resistance on the output stage of the amplifier across which the input voltage is applied via the output voltage may be selectively varied to change the current gain of the amplifier.

Abstract: A time stamp circuit comprises a plurality of counter programmable logic arrays for providing a Gray code count. Each count provided by the counters is associated as a time value with a specified event to be stored in memory. The count is generated automatically over a range of progressively slower frequencies provided by frequency dividing circuitry connected to an oscillator. The circuit has two modes of operation, a cumulative mode and a delta mode. In the cumulative mode, the count begins with the first occurrence of a specified event and ends when acquisition is halted. In the delta mode, a control programmable logic array automatically resets the Gray code count and thereby the clock frequency to its highest frequency each time a specified event is stored. The resolution, or time between counts, therefore is the same to begin between each pair of events.

Abstract: A power buffer circuit includes a power MOS device connected via a local feedback loop to a differential amplifier. The MOS device amplifies the power of an input signal to produce an output signal. The differential amplifier causes the output signal voltage to follow the input signal voltage by sensing a difference between the two voltages and generating in response a difference signal to the MOS device to change the output signal voltage level. The buffer circuit may be configured as a current source or a current sink that maintains unity voltage gain from the input to output signal. The power buffer circuit may be incorporated into a voltage regulator that maintains a remotely sensed output voltage substantially equal to a predetermined factor of a reference voltage via a second, outer feedback loop.

Abstract: A DC level shift circuit includes a differential amplifier with a level shift stage. The level shift stage has two portions for transmitting the input signals forming the differential signal through the level shift stage. A current source transmits the input signals through the level shift stage. Transistors with impedances substantially equal to the current source impedances are cross coupled to each input terminal. Each transistor senses a distortion signal produced by the current source impedance at one terminal and produces in response a correction signal. The correction signal is then transmitted to the other input terminal to be summed with the distortion signal there to pass the input signals through the level shift stage without distortion. The DC level shift stage is also responsive to another correction signal generated by a feedback control stage to control the common mode voltage of the amplifier.

Abstract: A method for automatically expanding and displaying a narrow pulse on an oscilloscope screen. The time sweep signal of the oscilloscope is first set to contain a predetermined number of input signal cycles. The speed of the time sweep is increased by an internal controller a number of settings to expand the signal cycle by a factor sufficient to place less than a single signal cycle within the sweep signal and an expanded singal pulse of greater than a specified duty factor outside the sweep signal. The dual trigger generators of the scope are set to trigger on opposite slopes of the pulse. If both trigger generators trigger, then the pulse is within the specified duty factor and the controller directs it to be displayed on the oscilloscope screen in its expanded form. The specified duty factor can be made exact by adjusting the duration of the sweep signal to match the duration of the duty factor once the period of the signal cycle is determined.

Abstract: An active low-pass filter especially suitable for inclusion in an integrated circuit and capable of operating at frequencies up to at least f.sub.T /.beta. of transistors within the filter. A bootstrap circuit is coupled to the emitter follower to reduce the capacitive effect of the emitter follower on the passed signal and to guarantee precision pass band gain match among the filters. A plurality of active filters may be connected across the signal path to provide a selection of bandwidths. A filter is switched into and out of the signal path by selectively enabling and disabling its current source.

Abstract: A current sensing circuit senses current and signals if such current exceeds a predetermined level within an etched circuit board. The circuit comprises a conductive trace of a predetermined resistance within a metallization layer of the board and a reference voltage circuit and comparator coupled to the trace. The reference voltage circuit senses voltage at first sense point on the trace and offsets the voltage a predetermined amount to form a reference voltage. The comparator senses voltage at a second sense point on the trace and compares it to the reference voltage. So long as the second voltage exceeds the reference voltage, the comparator indicates that the current is below the predetermined level. If the second voltage drops below the reference voltage, the comparator generates an output signal indicating that the current has exceeded the predetermined level.